Built-in self test circuit for testing cache tag array and...

Details Built-in self test circuit for testing cache tag array and... Built-in self test circuit for testing cache tag array and...

2005-11-22

2005-11-22

Verbrugge, Kevin (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S154000, C714S042000

Reexamination Certificate

active

06968427

ABSTRACT:
A cache memory comprising: 1) a tag array comprising a plurality of tag entry locations that are accessed by R of the M least significant bits of an N-bit received address and stored an address tag comprising the (N-M) most significant bits of the N-bit received address. The cache memory also comprises 2) cache hit comparison circuitry for comparing the (N-M) most significant bits of an N-bit received address with an address tag and generating a HIT signal if a match occurs, and 3) tag array test circuitry for testing the operation of the tag array and the cache hit comparison circuitry.

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