Horology: time measuring systems or devices – Time interval – Electrical or electromechanical
Reexamination Certificate
2008-07-15
2008-07-15
Miska, Vit W (Department: 2833)
Horology: time measuring systems or devices
Time interval
Electrical or electromechanical
C327S263000, C714S700000
Reexamination Certificate
active
10712925
ABSTRACT:
A circuit for measuring timing uncertainty in a clocked digital path and in particular, the number of logic stages completed in any clock cycle. A local clock buffer receives a global clock and provides a complementary pair of local clocks. A first local (launch) clock is an input to a delay line, e.g., 3 clock cycles worth of series connected inverters. Delay line taps (inverter outputs) are inputs to a register that is clocked by the complementary clock pair to capture progression of the launch clock through the delay line and identify any variation (e.g., from jitter, VDD noise) in that progression. Global clock skew and across chip gate length variation can be measured by cross coupling launch clocks from a pair of such clock buffers and selectively passing the local and remote launch clocks to the respective delay lines.
REFERENCES:
patent: 4494021 (1985-01-01), Bell et al.
patent: 4841551 (1989-06-01), Avaneas
patent: 5199008 (1993-03-01), Lockhart et al.
patent: 5309035 (1994-05-01), Watson et al.
patent: 5309111 (1994-05-01), McNeely et al.
patent: 5684760 (1997-11-01), Hunter
patent: 5793709 (1998-08-01), Carley
patent: 5936912 (1999-08-01), Kawabata et al.
patent: 6006025 (1999-12-01), Cook et al.
patent: 6058496 (2000-05-01), Gillis et al.
patent: 6111925 (2000-08-01), Chi
patent: 6205571 (2001-03-01), Camporese et al.
patent: 6311313 (2001-10-01), Camporese et al.
patent: 6316979 (2001-11-01), Keeth
patent: 6437713 (2002-08-01), Lesea
patent: 6493653 (2002-12-01), Drinkard et al.
patent: 6504414 (2003-01-01), Saeki
patent: 6801070 (2004-10-01), Gomm et al.
patent: 6822925 (2004-11-01), Van De Graaff
patent: 7034596 (2006-04-01), Andrews et al.
patent: 7219269 (2007-05-01), Frisch
patent: 2003/0108137 (2003-06-01), Li et al.
patent: 2003/0120456 (2003-06-01), Watson, Jr. et al.
patent: 2004/0049703 (2004-03-01), Maksimovic et al.
Franch Robert L.
Huott William V.
James Norman K.
Restle Phillip J.
Skergan Timothy M.
International Business Machines - Corporation
Law Office of Charles W. Peterson, Jr.
Miska Vit W
Percello, Esq. Louis J.
Verminski, Esq. Brian P.
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