Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2006-10-03
2006-10-03
Beausoliel, Robert (Department: 2113)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S033000, C714S715000, C714S718000, C714S719000
Reexamination Certificate
active
07117394
ABSTRACT:
A built-in self-test (BIST) circuit is configured to divide data output bits of a RAM macro into a plurality of groups each consisting of 2 bits, and provide a 1-bit comparator of a signature analyzer for each group to share one 1-bit comparator by respective two data output bits. A selector of a bit changer sequentially selects a data output bit from each group, and the 1-bit comparator sequentially compares output data for the selected data output bit with expected value data.
REFERENCES:
patent: 5555249 (1996-09-01), Hilley et al.
patent: 5557619 (1996-09-01), Rapoport
patent: 6301678 (2001-10-01), Sato et al.
Arent & Fox PLLC
Beausoliel Robert
Ehne Charles
Fujitsu Limited
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