Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2008-05-18
2010-10-12
Britt, Cynthia (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C702S118000
Reexamination Certificate
active
07814380
ABSTRACT:
Built-in self-test (BIST) architecture having distributed interpretation and generalized command protocol is disclosed. In an embodiment, a system is disclosed and includes a centralized built-in self-test (BIST) controller configured to store an algorithm to test a plurality of memory modules. The BIST controller stores the algorithm as a set of generalized commands that conform to a command protocol. The BIST controller is configured to send the set of generalized commands to a sequencer.
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International Search Report - OCT/US04/008664 - ISA/EPO - Aug. 23, 2004.
Written Opinion - OCT/US04/008664 - ISA/EPO - Aug. 23, 2004.
Averbuj Roberto Fabian
Hansquine David W.
Britt Cynthia
Kamarchik Peter M.
Pauley Nicholas J.
QUALCOMM Incorporated
Talpalatsky Sam
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