Built-in self-test arrangement for integrated circuit memory dev

Details Built-in self-test arrangement for integrated circuit memory dev Built-in self-test arrangement for integrated circuit memory dev

1997-04-30

1999-03-16

Nguyen, Viet Q.

Static information storage and retrieval

Read/write circuit

Testing

371 223, 371 221, 39518306, G01R 3128

Patent

active

058838430

ABSTRACT:
An integrated circuit has a built-in self-test (BIST) arrangement (60). The built-in self-test arrangement includes a read only memory (ROM), (140) that stores test algorithm instructions. A ROM logic circuit (410) receives an instruction read from the read only memory and produces a group of output signals dependent upon the instruction. A BIST register 420 receives and stores the group of output signals from the logic circuit for controlling self-test of the integrated circuit.

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