Built-in at-speed bit error ratio tester

Details Built-in at-speed bit error ratio tester Built-in at-speed bit error ratio tester

2005-06-01

2010-06-22

Ellis, Kevin L (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Error count or rate

C714S742000, C714S799000, C714S798000, C714S703000, C714S705000

Reexamination Certificate

active

07743288

ABSTRACT:
A built-in, at-speed BERT is provided that may be part of high-speed serial interface circuitry implemented on an integrated circuit. The built-in, at-speed BERT takes advantage of an existing clock data recovery (CDR) dual-loop architecture and built-in self test (BIST) circuitry. The built-in, at-speed BERT provides a low-cost solution for production testing of high-speed serial links, facilitating jitter analysis and evaluation of pre-emphasis and equalization performance. This further allows adaptation of pre-emphasis and equalization.

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