Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2005-03-28
2008-08-12
Chaudhari, Chandra (Department: 2891)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S977000, C257SE21704
Reexamination Certificate
active
07410841
ABSTRACT:
A method (10) of forming fully-depleted silicon-on-insulator (FD-SOI) transistors (150) and partially-depleted silicon-on-insulator (FD-SOI) transistors (152) on a semiconductor substrate (104) as part of an integrated circuit fabrication process is disclosed.
REFERENCES:
patent: 6222234 (2001-04-01), Imai
patent: 6537891 (2003-03-01), Dennison et al.
patent: 2004/0180478 (2004-09-01), Yang et al.
patent: 2004/0217420 (2004-11-01), Yeo et al.
patent: 2004/0217775 (2004-11-01), Turner
U.S. Appl. No. 11/091/078, filed Mar. 28, 2005, Tigelaar.
Brady III Wade J.
Chaudhari Chandra
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
LandOfFree
Building fully-depleted and partially-depleted transistors... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Building fully-depleted and partially-depleted transistors..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Building fully-depleted and partially-depleted transistors... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4006000