Patent
1990-08-27
1991-10-22
Makay, Albert J.
98 345, 98 315, B01L 104, F24F 707
Patent
active
050584910
ABSTRACT:
A building for the manufacture of integrated circuits which includes a manufacturing equipment floor with processing equipment for the manufacture of integrated circuits, a floor under the manufacturing floor has supporting equipment associated with each of the processing equipment, and an upper floor above the manufacturing floow supports a plenum system that provides at least two classes of clean air circulation to the manufacturing floor. Each piece of processing equipment is enclosed with means to separate it from the surrounding air. A clean air input of the highest class of clean air purity is provided to the processing equipment in the enclosure. The air/gas exhaust is directed through an air/gas handling system. Means are also provided to provide the surrounding areas a clean air input of a lower class of clean air purity from the plenum system and the air/gas exhaust directed to an air/gas handling system. Interchangeable means are provided that are associated with the plenum system which quickly allow the change of air purity to another class of clean air purity whereby the processing equipment can be removed, replaced with another processing equipment or a new piece of processing equipment inserted without undue down time of the manufacturing of the integrated circuits.
REFERENCES:
patent: 2912918 (1959-11-01), Mead
patent: 4489881 (1984-12-01), Dean et al.
patent: 4534389 (1985-08-01), Tullis
patent: 4549472 (1985-10-01), Endo et al.
patent: 4608066 (1986-08-01), Cadwell, Jr.
patent: 4674936 (1987-06-01), Bonora
patent: 4676144 (1987-06-01), Smith, III
patent: 4693173 (1987-09-01), Saiki et al.
patent: 4699640 (1987-10-01), Suzuki et al.
patent: 4724874 (1988-02-01), Parikh et al.
patent: 4781511 (1988-11-01), Harada et al.
patent: 4826360 (1989-05-01), Iwasawa et al.
patent: 4838150 (1989-06-01), Suzuki et al.
"VTC Submicron CMOS Factory" Wilton Workman and Lloyd Kavan 10-87 Microcontamination.
"Defect Density Reduction in a Class 100 Fab Utilizing the Standard Mechanical Interface" Stephen Titus et al, 11-87 Solid State Technology.
Buhler James E.
Laub Helmut A.
Simon Rudolf O.
Wiemer Klaus C.
Doerrler William C.
Makay Albert J.
Saile George O.
Taiwan Semiconductor Manufacturing Company , Ltd.
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