Build-up structures with multi-angle vias for chip to chip...

Details Build-up structures with multi-angle vias for chip to chip... Build-up structures with multi-angle vias for chip to chip...

2005-07-19

2005-07-19

Ngo, Hung V. (Department: 2831)

Electricity: conductors and insulators

Boxes and housings

Hermetic sealed envelope type

C257S738000, C257S780000, C257S778000, C257S774000

Reexamination Certificate

active

06919508

ABSTRACT:
A build-up structure for chip to chip interconnects and System-In-Package utilizing multi-angle vias for electrical and optical routing or bussing of electronic information and controlled CTE dielectrics including mesocomposites to achieve optimum electrical and optical performance of monolithic structures. Die, multiple die, Microelectromechanical Machines (MEMs) and/or other active or passive components such as transducers or capacitors can be accurately positioned on a substrate such as a copper heatsink and multi-angle stud bumps can be placed on the active sites of the components. A first dielectric layer is preferably placed on the components, thereby embedding the components in the structure. Through various processes of photolithography, laser machining, soft lithography or anisotropic conductive film bonding, escape routing and circuitry is formed on the first metal layer. Additional dielectric layers and metal circuitry are formed utilizing multi-angle vias to form escape routing from tight pitch bond pads on the die to other active and passive components. Multi-angle vias can carry electrical or optical information in the form of digital or analog electromagnetic current, or in the form of visible or non-visible optical bussing and interconnections.

REFERENCES:
patent: 6518090 (2003-02-01), Saza et al.
patent: 6632028 (2003-10-01), Yang et al.
patent: 6657124 (2003-12-01), Ho
patent: 6753208 (2004-06-01), MacIntyre
patent: 6781244 (2004-06-01), MacIntyre

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