Build-up board package for semiconductor devices

Details Build-up board package for semiconductor devices Build-up board package for semiconductor devices

2000-01-20

2002-01-22

Whitehead, Jr., Carl (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With contact or lead

C257S698000, C257S690000, C257S678000, C257S773000

Reexamination Certificate

active

06340841

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a package for semiconductor devices.
2. Description of the Related Art
It is a growing trend to use a package for semiconductor devices in the form of a build-up board composed of a core board having multilayer wiring patterns formed on both sides by build-up process.
FIG. 1
shows a build-up board
10
having a core board
12
of an insulating material having base wiring patterns
13
and
14
formed on both sides and electrically connected to each other by a throughhole plated coating
15
.
Insulating layers
16
and
17
are formed on the base wiring patterns
13
and
14
, respectively, and contain viaholes
16
a
and
17
a.
Electroless and the subsequent electrolytic plating treatments are conducted to form a copper plated coating on the insulating layers
16
and
17
and the side walls of the viaholes
16
a
and
17
a.
The copper plated coating is then patterned by etching to form upper wiring patterns
18
and
19
, as a first layer, which are connected to the base wiring patterns
13
and
14
through the copper plated coating of the viaholes
16
a
and
17
a.
The process is repeated to form a multilayer wiring patterns on both sides of the core board
12
.
The outermost wiring pattern
20
on the front side of the core board
12
has pads to which a semiconductor chip
21
is bonded by flip-chip bonding.
The outermost wiring pattern
22
on the back side of the core board
12
has external connection terminals on which solder bumps
23
are formed for external connection.
The throughholes and viaholes are filled with a resin and the front and back surfaces are covered with solder resist layers
24
,
24
for protection.
The build-up board
10
is advantageous because insulating layers are formed by application of a resin to provide a structure with a small height and the wiring patterns
18
,
19
,
20
and
22
are formed by plating to allow fine patterning, both enabling mounting of a high density semiconductor chip
21
.
However, there is a problem in that the process requires a large number of steps causing an increased cost when forming insulating layers on both sides of a core board
12
by application of a resin or other materials, boring viaholes in each of the insulating layers by laser machining or other methods, plating and etching to form a wiring pattern on each of the insulating layers.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a package for semiconductor devices which can be produced in a reduced number of steps with a reduced cost.
To achieve the object according to the present invention, there is provided a package for semiconductor devices, comprising:
a core board having a front side with a front side base wiring pattern formed thereon and a back side with a back side base wiring pattern formed thereon, the front and back side wiring patterns being electrically connected to each other through a conductor segment penetrating the core board;
a front side laminate of upper wiring patterns with intermediate insulating layers intervening therebetween on the front side base wiring pattern, in which each adjacent pair of the upper wiring patterns are electrically connected to each other through a via plated coating on a side wall of viaholes penetrating one of the intermediate insulating layers that intervenes between the adjacent pair and an outermost one of the upper wiring patterns is patterned for electrical connection to a semiconductor chip;
a back side laminate of insulating layers on the back side base wiring pattern; and
an external connection wiring pattern including external connection terminals on the back side laminate of insulating layers, wherein the external connection wiring pattern is electrically connected to the back side base wiring pattern through a via penetrating the back side laminate of insulating layers.
The present inventive structure provides a reduced number of production steps and a reduced production cost because there are no wiring patterns within the back side laminate of insulating layers, except for optional power or ground planes.
It is advantageous if the intermediate insulating layers on the front side of the core board and the insulating layers of the back side laminate are in the same number to provide similar structures on both sides of the core board, thereby preventing distortion of the core board or a completed package.
The via penetrating the back side laminate of insulating layers may be either formed of a plated coating on a side wall of viaholes penetrating the back side laminate of insulating layers, or formed of a conductor segment filling the viaholes.
The package may include bumps formed on the external connection terminals.
The package may optionally include a power plane or a ground plane which intervenes between the insulating layers of the back side laminate and is electrically connected to the via penetrating the back side laminate.


REFERENCES:
patent: 5473120 (1995-12-01), Ito et al.
patent: 5714801 (1998-02-01), Yano et al.
patent: 6081026 (1998-11-01), Wang et al.
patent: 5892273 (1999-04-01), Iwasaki et al.
patent: 5901050 (1999-05-01), Imai
patent: A-7-106464 (1995-04-01), None
patent: A-9-18150 (1997-01-01), None

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