Buffering for an I.sup.2 L memory cell

Details Buffering for an I.sup.2 L memory cell Buffering for an I.sup.2 L memory cell

1976-11-04

1978-07-04

Konick, Bernard

Static information storage and retrieval

Systems using particular element

Flip-flop

307238, 365206, G11C 1140

Patent

active

040992632

ABSTRACT:
A memory cell having input and output buffering. Input buffering is provided by connecting the injector input of an integrated injection logic (I.sup.2 L) gate to the data input line of the memory cell and by connecting the injector input of the input gates of the memory cell to the write enable line. In order to enter data into the memory cell, the input gates must be energized via the injector input. Output buffering is provided by placing another integrated injection logic gate between the memory cell output and the data output line. The injector input of the another gate is connected to a read select line thereby permitting information contained within the memory cell to be read out to the data output line whenever the read select line connected to the injector input is enabled.

REFERENCES:
patent: 3986178 (1976-10-01), McElroy et al.

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