Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2000-09-18
2004-11-16
Auve, Glenn A. (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C711S105000, C365S052000
Reexamination Certificate
active
06820163
ABSTRACT:
BACKGROUND
The present disclosure relates to providing data buffers in an interface between a chipset and memory modules.
Computer systems often contain one or more integrated circuit (IC) chips that are coupled to memory modules using a memory interface. These IC chips may be controllers referred to as chipsets. The memory interface provides communication between the IC chipset (e.g. the CPU) and the memory modules. The memory interface may contain address bus lines, command signal lines, and data bus lines. Increasing demand for higher computer performance and capacity has resulted in a demand for a larger and faster memory. However, as the operating speed and the number of memory modules connected to the chipset increase, the increased capacitive loading may place substantial limit on the amount and speed of memory.
Prior art designs, such as a registered dual in-line memory module (DIMM), have addressed the above-described difficulties by providing an address/command buffer in the address bus lines and the command signal lines to relieve the capacitive loading effects. Karabatsos (U.S. Pat. No. 5,953,215) describes a loading relief design for the data bus lines by providing FET switches in the interface between the chipset and the memory modules.
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Cover Sheet, FIGS. 20A and 20B, and Cols. 41-44 of US Patent No. 6,345,321 to Litaize, et al.
Bonella Randy M.
Dodd Jim M.
Halbert John B.
Lam Chung
McCall James A.
Auve Glenn A.
Intel Corporation
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