Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2007-07-24
2007-07-24
Bragdon, Reginald (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C710S052000, C710S310000, C711S105000
Reexamination Certificate
active
10777921
ABSTRACT:
Providing electrical isolation between the chipset and the memory data is disclosed. The disclosure includes providing at least one buffer in a memory interface between a chipset and memory modules. Each memory module includes a plurality of memory ranks. The buffers allow the memory interface to be split into first and second sub-interfaces. The first sub-interface is between the chipset and the buffers. The second sub-interface is between the buffers and the memory modules. The method also includes interleaving output of the buffers, and configuring the buffers to properly latch the data being transferred between the chipset and the memory modules. The first and second sub-interfaces operate independently but in synchronization with each other.
REFERENCES:
patent: 5572691 (1996-11-01), Koudmani
patent: 5757712 (1998-05-01), Nagel et al.
patent: 5768624 (1998-06-01), Ghosh
patent: 5828892 (1998-10-01), Mizuta
patent: 5926838 (1999-07-01), Jeddeloh
patent: 5953215 (1999-09-01), Karabatsos
patent: 6345321 (2002-02-01), Litaize et al.
patent: 6493776 (2002-12-01), Courtright et al.
patent: 6502161 (2002-12-01), Perego et al.
patent: 6553450 (2003-04-01), Dodd et al.
patent: 2001/0052057 (2001-12-01), Lai et al.
patent: 0691617 (1996-01-01), None
patent: 2000231784 (2000-08-01), None
patent: WO 99/30240 (1999-06-01), None
Pohm et al., “The Cost and Performance Tradeoffs of Buffered Memories”, Proceedings of the IEEE, Aug. 1975, IEEE, vol. 63, Is. 8, pp. 1129-1135.
Cover page and search report of International Publication No. WO 02/023355, 5 pages.
Cover page and search report of International Publication No. WO 02/023355 (revised version), 5 pages.
Bonella Randy M.
Dodd Jim M.
Halbert John B.
Lam Chung
Bragdon Reginald
Intel Corporation
Pedigo Philip A.
Willhite Tyler
LandOfFree
Buffering and interleaving data transfer between a chipset... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Buffering and interleaving data transfer between a chipset..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Buffering and interleaving data transfer between a chipset... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3783294