Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
1998-02-10
2001-08-21
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S034000, C326S033000
Reexamination Certificate
active
06278295
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention generally pertains to the field of input buffers. In particular, the present invention relates to input buffers having a stable trip point, to reference voltage generators which are responsive at least to process skew and supply voltage variations and that may be used in such input buffers. The present invention also pertains to methods of stabilizing trip points of input buffers over at least supply voltage variations and process skew.
2. Description of the Related Art
Input buffers, such as TTL input buffers, are interface circuits used to convert Transistor-Transistor Logic (TTL) signal levels to Complementary Metal Oxide Semiconductor (CMOS) signal levels. An ideal input buffer would have a trip point set to a nominal Vcc/2 for a low input voltage level (VIL) of 0 volts and a high input voltage level (VIH) of Vcc volts. Moreover, the trip point of such an ideal input buffer would be utterly stable and would be insensitive to process parameter skew, variations in the supply voltage Vcc, temperature and other manufacturing and environmental variations.
The performance of currently available input buffers only approximates that of such an ideal input buffer. A number of factors affect this performance and act alone and in combination to cause the trip point to vary from its nominal value of Vcc/2. A stable trip point, however, is important whenever set up and hold issues arise. For example, when latching an address in a register, the address must remain stable during the set up time interval as well as during the hold time interval. If the clock pulse arrives too late, i.e., in violation of hold time, the address to be latched will have disappeared and no address will have been latched. Conversely, should the clock pulse arrive too early, the address will not have stabilized yet and again no valid data will be latched within the register. The situation also holds in asynchronous circuits wherein the clock signal is typically an active low Write Enable (WEB) signal. IN this case, data is not latched to a register but rather if the address changes too close to the WEB pin being asserted, the previously asserted address may be inadvertently overwritten with the new data.
This set up and hold window is typically very short. For example, the Set Up time interval (t
sa
) may be on the order of about 2.5 ns, whereas the Hold time interval (t
ha
) may be on the order of about 0.5 ns. The total time interval during which the address to be latched must remain stable is the sum of these two intervals and is, therefore, only about 2.5 ns in duration. Variations in the input buffer trip point cut into this very narrow window and are, therefore, undesirable. The reason for this is illustrated in FIG.
7
. The top signal in
FIG. 7
is a clock pulse that is active on its positive going edge. In
FIG. 7
, the nominal trip point is set to be 1.25 volts. Then, a 250 mV variation in the trip point sets the new trip point at 1.5 V. This 250 mV variation, however, has a different effect upon positive going address pulses than it does on negative going address pulses. As shown in
FIG. 7
, the positive going address pulse will not reach the new 1.5 V trip point until later in time than will the negative going address pulse, the bottom signal in FIG.
7
. In other words, the negative going address pulses will trip sooner than the positive going address pulse, thus making all falling edges faster and all rising edges slower. There is thus an asymmetry in the threshold point at which the signals trip.
If the slope of the pulse shown in
FIG. 7
is 1V
s, a variation in the trip point of 0.25 volts means 250 ps of time. From
FIG. 7
, it can be seen that the actual penalty for a 250 mV variation from the nominal trip point is 500 ps, as the positive going address pulse trips 250 ps after it would have at the nominal trip point, whereas the negative going address pulse trips 250 ps before it would have at the nominal trip point. Therefore, the Set Up and Hold window of 2.0 ns has been decreased by about 500 ps, fully one quarter of the available window. This decreased set up and hold window imposes additional and more severe timing constraints upon the operation and design of the input buffer, and may cause invalid data to be latched, depending on the magnitude of the variation in the trip point. Indeed, variations from the nominal trip point of greater magnitude quickly cut into the available set up and hold time interval. For example, a variation in the trip point that is only 50 mV greater than that illustrated in
FIG. 7
reduces the Set Up and Hold window to only about 1.4 ns.
There are a number of reasons why the DC trip point of an input buffer would stray from nominal data book specifications. In the case of a CMOS buffer stage similar in design to that shown in
FIG. 1
, it has been found that variations in the magnitude of the Vcc supply and skew in a number of critical process parameters are responsible for about 70% and 20% of the trip point variation, respectively. The remaining 10% of the observed DC trip point variation is generally attributed to temperature fluctuations. The more important of these critical process parameters, in terms of contributing to trip point variations, are believed to be the critical dimensions, such length and width, of the transistor gate (hereafter “Gate CD” or “Poly CD” if polysilicon is used for the gate), the field oxide critical dimensions (hereafter “FOM CD”, for Field Oxide Mask Critical Dimensions) and the threshold voltage adjust dose (hereafter Vt adjust dose). Of these three process parameters, only the Vt adjust dose is believed to affect n channel and p channel FETs differently, although for narrow devices only, FOM CD can affect n and p channel devices differently, due to encroachment of field implants into the channel.
In submicron silicon gate processes, the speed of the device appears to be heavily dependent upon the gate etch step. When using polysilicon as the gate material, if the gate is under or over etched by as little as 10%, the speed of the device may be greatly affected. This is because the gate etch step defines the length of the channel L and the speed of the resultant device is proportional to the aspect ratio (W/L), where W is the width of the channel region and L its length. This (W/L) term affects the speed of the device, whether the device is operating in the linear region (also called the triode region) or is operating in the saturation mode. For example, the gate may have been over-etched during fabrication, resulting in shorter than expected n channel and p channel device channel lengths, thus causing these devices to have a greater Ids and speed than nominal.
The filed oxide is an isolation structure (generally a LOCOS or shallow trench isolation structure comprising silicon oxide) and defines the device width W of the (W/L) term by separating the active regions of CMOS devices. Variations in the FOM CD affect both n and p channel transistors.
The effects of the V adjust dose, however, are not shared equally among n channel FETs and p channel FETs. The Vt adjust dose raises the threshold voltage Vt by implantation of a p-type material such as boron into the channel region, before the polysilicon layer is formed. The boron dose is critical, as it has a direct affect upon Vt, which is directly related to the speed of the device. For example, a particular batch of wafers may have been given a slightly larger than nominal Vt adjust dose during fabrication. The p channel devices of such a batch may have a lower Vt then the n channel devices. A lower threshold voltage Vt results in higher drain to source current Ids for a given gate to source voltage Vgs. Higher Ids correlates directly with device speed.
The process parameters discussed above create so-called process corners in which p channel and n channel devices are termed slow, fast or typical. It is common to refer to these corners as ss, sf, ff and fs, where the first letter refers to the speed of the p c
Cypress Semiconductor Corp.
Maiorana P.C. Christopher P.
Tokar Michael
Tran Anh
LandOfFree
Buffer with stable trip point does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Buffer with stable trip point, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Buffer with stable trip point will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2445320