Buffer with inductance-based capacitive-load reduction

Details Buffer with inductance-based capacitive-load reduction Buffer with inductance-based capacitive-load reduction

2006-09-25

2010-06-01

Cho, James H. (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S081000, C326S088000, C327S108000, C327S111000

Reexamination Certificate

active

07728629

ABSTRACT:
A buffer circuit uses (e.g., active) inductors for driving capacitive loads. In one embodiment, the buffer circuit has one or more stages, each stage having one CMOS inverter. Each CMOS inverter has one NMOS transistor and one PMOS transistor and is coupled to a stage input and a stage output. Additionally, at least one stage of the buffer circuit has two inductors, each coupled between a different voltage reference for the buffer circuit and the stage output. One inductor has a PMOS transistor coupled to the gate of an NMOS transistor and the other inductor has an NMOS transistor coupled to the gate of a PMOS transistor. When driving capacitive loads, the inductors partially tune out the apparent load capacitance CL, thereby improving the charging capabilities of inverter and enabling quicker charge and discharge times. Furthermore, partially tuning out apparent load capacitance facilitates the driving of larger capacitive loads.

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Apinunt Thanachayanont, CMOS Transistor-Only Active Inductor for IF/RF Applications, Dec. 2002, IEEE ICIT'02, p. 1212 Fig. 2.
Apinunt Thanachayanont, CMOS Tansistor Only Active Inductor for IF/RF Applications, Dec. 2002, IEEE ICIT'02, p. 1212 Fig. 2.
Apinunt Thanachayanont, CMOS Transistor Only Active Indcutor for IF/RF Applications, Dec. 2002, IEEEE ICIT'02, p. 1212 Fig. 2.
“CMOS Digital Integrated Circuits Analysis and Design,” by Sung-Mo Kang and Yusuf Leblebigi, Second Edition, Chapter 8, pp. 251-253.
“Digital Integrated Circuits, A Design Perspective,” by Jan M. Rabaey, Prentice Hall Electronics and VLSI Series, Chapter 8, pp. 450-451.
“CMOS Transistor-Only Active Inductor For IF/RF Applications,” by Apinunt Thanachayanont; IEEE ICIT'02, Bangkok, Thailand, pp. 1209-1212.

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