Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
2000-03-07
2001-05-29
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S017000, C326S086000
Reexamination Certificate
active
06239618
ABSTRACT:
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable.
I. CROSS-REFERENCE TO RELATED APPLICATIONS
(Not Applicable)
II. STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH
(Not Applicable)
III. BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is directed generally to a buffer and, more particularly, to a buffer with a fast edge propagation.
2. Description of the Background
In a device, such as a semiconductor device, it is desirable to include a buffer which buffers the device input signals before they are communicated to the internal circuitry of the device. A buffer typically adapts the device input signals to internally required signal properties, such as signal voltage levels and transition delays, that must be present for internal circuitry to operate correctly. On devices which contain certain circuits, such as wide random access memory (RAM) circuits, input buffers must be placed around the die because the input/output pads are spread around the device.
When input buffers buffer certain time-dependent signals, such as the system clock signal input to a double data rate RAM, it is important to have a fast clock to data time (i.e. tKQ, tKHQV, and clock to out prop delay) on both edges of the clock. When conventional buffers, PLL circuits, or DLL circuits are used in such applications, there is no manner in which to stop the clock, there is excess capacitance on the lines, and there is a certain amount of clock distortion. Thus, there is a need for a buffer that can provide a fast clock to data time while allowing for clock stopping, providing low capacitance on the lines, and introducing a minimal amount of clock distortion.
IV. SUMMARY OF THE INVENTION
The present invention is directed to a buffer having first and second input terminals and an output terminal. The buffer includes a fast edge driver having an input terminal and an output terminal, with the input terminal connected to the first input terminal of the buffer, and the output terminal connected to the output terminal of the buffer. A shielding circuit is provided having an input terminal and an output terminal, with the input terminal connected to the second input terminal of the buffer. The buffer further includes a recovery circuit having an input terminal and an output terminal, with the input terminal connected to the output terminal of the shielding circuit, and the output terminal connected to the output terminal of the buffer.
The present invention is also directed to a method of propagating a first input signal. The method includes receiving the first input signal, receiving a second input signal, producing a delayed second input signal, driving the first input signal when a first input transition occurs, recovering the first input signal when a second transition occurs, and propagating the first input signal after one of the first and second input transitions occur.
The present invention represents a substantial advance over prior buffers. For example, the present invention has the advantage that it allows for clock stopping. Thus, qualified clocks can be used with the present invention, e.g. for part selection. The present invention also has the advantage that it provides for low capacitance on the lines. The present invention has the further advantage that it introduces a minimal amount of clock distortion.
REFERENCES:
patent: 4647797 (1987-03-01), Sanwo et al.
patent: 5410262 (1995-04-01), Kang
patent: 5489858 (1996-02-01), Pierce et al.
patent: 5612630 (1997-03-01), Wright et al.
patent: 5701090 (1997-12-01), Hidaka et al.
patent: 5963047 (1999-10-01), Kwong et al.
Porter John D.
Thompson William N.
Weber Larren G.
Chang Daniel D.
Kirkpatrick & Lockhart LLP
Micro)n Technology, Inc.
Tokar Michael
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