Buffer with controlled hysteresis

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Input noise margin enhancement

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Details

326 32, 326 34, 326 83, 327206, 327513, H03K 190948, H03K 1716

Patent

active

056546459

ABSTRACT:
A method and apparatus that controls and modulates the amount of hysteresis in a buffer in response to changes in operating conditions. The buffer comprises a first stage switching element and a hysteresis control element. The first stage switching element is configured to have a DC voltage trip point. As an input voltage, transitioning from a first state to a second state, is applied to the first stage switching element, the first stage switching element transitions as the input voltage reaches the DC voltage trip point. The transition of the first stage switching element enables the hysteresis control element to provide a feedback path biasing the first stage switching element. Consequently, as the input voltage transitions from the second logic level to the first logic level, the first stage switching element transitions at a voltage level offset from the DC trip point to provide hysteresis in the buffer. The hysteresis control element further controls and modulates the amount of hysteresis in the buffer such that when the buffer is operating under high noise conditions, the hysteresis in the buffer is a maximum amount and when the buffer is operating under low noise conditions, the hysteresis in the buffer is a minimum amount. Alternatively, the hysteresis control element, in addition to the maximum and minimum hysteresis amounts, provides an intermediate amount of hysteresis when the buffer is operating under an intermediate noise condition.

REFERENCES:
patent: 5334883 (1994-08-01), Rosenthal
patent: 5336942 (1994-08-01), Khayat
patent: 5341033 (1994-08-01), Koker
patent: 5349246 (1994-09-01), McClure
patent: 5369311 (1994-11-01), Wang et al.
patent: 5399960 (1995-03-01), Gross

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