Buffer with adjustable slew rate and a method of providing an ad

Details Buffer with adjustable slew rate and a method of providing an ad Buffer with adjustable slew rate and a method of providing an ad

1998-08-05

2000-12-05

Tokar, Michael

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

326 21, 326 17, 326 83, 326 86, 327170, 327525, H03K 1716, H03K 512

Patent

active

061572047

ABSTRACT:
A buffer with an adjustable slew rate, including a current driver having an input terminal and an enable circuit connected to the input terminal to selectively enables the current driver. In one embodiment, the current driver includes an input terminal and the enable circuit includes a memory element, the state of which is used to activate the enable signal, a read circuit which reads the state of the memory element, a latch which latches the signal from the read circuit, and an output circuit connected to the input terminal of the current driver which provides a signal which selectively enables the current driver to adjust the slew rate.

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