Buffer to multiply memory interface

Details Buffer to multiply memory interface Buffer to multiply memory interface

2000-09-18

2003-04-22

Nguyen, Hiep T. (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S157000, C711S168000, C710S052000

Reexamination Certificate

active

06553450

ABSTRACT:

BACKGROUND
The present disclosure relates to providing data buffers in an interface between a chipset and multiple ranks of memory modules.
Computer systems often contain one or more integrated circuit (IC) chips (chipset) that are coupled to memory modules using a memory interface. The memory interface provides communication between the IC chipset (e.g. the CPU) and the memory modules. The memory interface may-contain address bus lines, command signal lines, and data bus lines. Increasing demand for higher computer performance and capacity has resulted in a demand for a larger and faster memory. However, as the operating speed and the number of memory modules connected to the chipset increase, the increased capacitive loading may place a substantial limit on the amount and speed of memory.
Prior art designs, such as a registered dual in-line memory module (DIMM), have addressed the above-described difficulties by providing an address/command buffer in the address bus lines and the command signal lines to relieve the capacitive loading effects. Karabatsos (U.S. Pat. No. 5,953,215) describes a loading relief design for the data bus lines by providing FET switches in the interface between the chipset and the memory modules.
In the prior art design
100
of
FIG. 1
, the interface
108
between the chipset
102
and the memory modules
104
is unbuffered. In some embodiments, the memory modules
104
may be individually mounted on memory boards
106
as shown. In other embodiments, the memory modules
104
may be soldered directly onto the same motherboard as the chipset
102
.
In the prior art design
100
, the chipset
102
is configured to receive two supply voltages, 1.0 volt (low) and 1.5 volts (high). The high voltage is necessary on the chipset side to provide compatible driving voltage on the memory interface
108
. Further, the pin count on the chipset
102
may be designed to be 2x in order to provide a particular memory access rate or frequency, such as &ohgr;).


REFERENCES:
patent: 5572691 (1996-11-01), Koudmani
patent: 5768624 (1998-06-01), Ghosh

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