Buffer system with reduced interference

Details Buffer system with reduced interference Buffer system with reduced interference

1993-06-15

1995-03-14

Westin, Edward P.

Electronic digital logic circuitry

Interface

Current driving

326122, 326 21, 327307, H03K 190175, H03K 19094

Patent

active

053979400

ABSTRACT:
A system comprising an output buffer circuit and an input buffer circuit in which the output buffer circuit appreciably reduces the level of the signal to be transmitted between the two buffer circuits so as to, which corresponds to U.S. Pat. No. 4,305,009, disturbing signals in the output buffer circuit. These disturbing signals occur as a result of high peak currents during voltage transitions in the input signal, after which the original level is restored in the input buffer circuit. To further reduce the effect of disturbing signals, a reference voltage level, which is largely free of disturbing signals and relative to which the output signals of the output buffer circuit are determined, is likewise transmitted to the input buffer circuit. To increase the edge steepness of the signal to be transmitted, a series combination of an inverter and a capacitive voltage divider is coupled between the input of the output buffer circuit and the input of the input buffer circuit. Finally, the input buffer circuit comprises means for reducing the offset voltage.

REFERENCES:
patent: 4002928 (1977-01-01), Goser et al.
patent: 4045691 (1977-08-01), Asano
patent: 4998028 (1991-03-01), Chappell et al.
patent: 5023488 (1991-06-01), Gunning
patent: 5198699 (1993-03-01), Hashimoto et al.

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