Buffer switch having descriptor cache and method thereof

Details Buffer switch having descriptor cache and method thereof Buffer switch having descriptor cache and method thereof

2005-09-06

2005-09-06

Shin, Christopher B. (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Data transfer specifying

C710S022000, C710S052000, C709S212000, C370S412000

Reexamination Certificate

active

06941392

ABSTRACT:
A buffer switch comprises a data memory that stores a plurality of data. A cache memory comprises a plurality of FIFO mini-queues each storing a plurality of descriptors each corresponding to a respective one of the plurality of data. An output memory comprises a plurality of output queues. A burst writer simultaneously transfers M ones of the plurality of descriptors stored in a corresponding one of the plurality of mini-queues to at least a corresponding one of the plurality of output queues. The burst writer accesses the output memory, when the output memory is available, once for every M ones of the plurality of descriptors.

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