Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1998-09-29
2001-07-10
Beausoleil, Robert (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S120000, C710S120000, C710S022000
Reexamination Certificate
active
06260095
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a method for translating operations from one bus to another bus and more particularly to a buffer reservation mechanism for optimally transferring data between buses.
2. Description of the Related Art
Personal computers are constantly changing as new technologies evolve and are incorporated into the computer. Performance improvements in the microprocessor and memory have resulted in computers so powerful that they are now capable of performing tasks that before could only be performed by large mainframe computers. However, to fully replace a mainframe computer, the computer must have significant memory and storage capacity supported by a hearty I/O (input/output) subsystem.
Several standardized I/O buses are available to the system designer including: ISA (Industry Standard Architecture); EISA (Extended Industry Standard Architecture); and PCI (Peripheral Component Interface). Today's computers are typically designed with some combination of the three. For moving data between the buses, a bridge device is typically provided.
The bridge device connects to both buses for transferring data between the buses and translating the bus control signals. The buses can be different, or especially in the case of PCI, the bridge can simply provide an electrical extension to the same logical bus. This electrical separation makes it possible to meet the PCI bus requirement of limiting the number of physical devices on one bus segment, while at the same time not limiting the total number of PCI agents. In PCI bus vernacular, an agent is the term denoting the class of devices connecting to the bus, including master and slave devices.
These buses all support a scheme called bus mastering wherein a device or agent, usually other than the processor, may request an arbiter for control of the bus. If the arbiter grants the agent control, the agent becomes a bus master. The bus master directs its operations to another agent called a slave. The bus master may then perform operations without processor intervention much more efficiently than if the processor were involved. Many times a master on an origination bus will communicate with a slave on a destination bus. If the buses are coupled by a bridge, the performance of the bridge greatly effects the performance of the communication between the master and slave. Thus, it is desirable to optimize this pathway.
In the case of the PCI bus, one method of improving performance is to permit delayed transactions or read posting. More details on the PCI bus and on Delayed Transactions are found in the PCI Local Bus Specification version 2.1 which can be obtained from the PCI Special Interest Group, Hillsboro, Oreg. The PCI Local Bus Specification and its related documentation are hereby incorporated by reference. Delayed transactions permit the bus to be used while a slow device is preparing data in response to a request. Thus, instead of the slow device applying wait states to the bus, the bus may be used for other requests. For a bridge, the destination bus means the interface that was not acting as the target of the original request. A delayed transaction progresses to completion in three phases: the request by the master; completion of the request by the target; and the completion of the transaction by the master.
In the first phase, the master generates a transaction on the bus, the target decodes the access, latches the information required to complete the access and terminates the request with a retry-termination. Since the master cannot distinguish between a target which is completing the transaction using delayed transaction termination and a target which simply cannot complete the transaction at the current time, it must reissue the request. During the second phase, the target independently completes the request on the destination bus using the latched information from the delayed request. If the delayed request is a read, the target obtains the requested data and completion status. If the delayed request is a write, the target delivers the write data and obtains the completion status. During the third phase, the master successfully rearbitrates for the bus and reissues the original request. The target decodes the request and provides the master with the completion status (and data if a read request). All bus commands that must complete on the destination bus before completing on the originating bus may be completed as a delayed transaction. These include interrupt acknowledge, I/O read, I/O write, configuration read, configuration write, memory read, memory read line and memory read multiple commands. Memory write and memory write and invalidate commands can complete on the originating bus before completing on the destination bus. These commands are not completed using delayed transactions termination and are normally posted.
One such bridge device is the Intel PCI to EISA bridge chip set. The 82375EB/SB PCI-EISA Bridge and the 82374EB/SB EISA system component work in tandem to provide an EISA I/O interface for computers having a PCI bus. The chip set can be either a master or slave on both the PCI and EISA buses. For PCI to EISA data transfers, four 32-bit posted write buffers are provided to enhance single cycle PCI bus transactions. For EISA to PCI data transfers, four 16-byte line buffers are included to support EISA bursting.
In order to use both buses efficiently, most bridges implement some amount of data buffering within the bridge itself. This allows the bridge to de-couple the buses from each other and let each bus run at its maximum speed without being slowed down by the other. There are generally two types of buffers that may be implemented in a bridge: write posting buffers and read prefetch or read ahead buffers. Both types can be implemented on either bus.
Write posting buffers accept write data from one bus and acknowledge reception to that bus. This frees the bus to perform other transactions. The bridge temporarily stores, or posts, the write data until it can be written to the other bus. Read prefetch buffers take the address from a single read access and read additional data speculating that it will also be needed. The bridge then holds that data in a buffer until it is either unusable or it is used by a read access.
In the Intel chip set, the buffer permits the bridge to receive short bursts of data at peak data transfer rates. For example, if a EISA device requests data from memory on the PCI bus, the bridge can burst four 32-bit data words from the PCI memory into its buffer and then release the PCI bus to other PCI requesters while the EISA device reads the buffers. Therefore, the PCI bus is not held up by the EISA device. While the buffer is filled, the EISA device is notified to read the data from the buffer. The EISA device may then read the data from the buffer at its burst transfer speed. Thereafter, the bridge attempts to keep up with the EISA bus transfer rate by performing short burst of data across the PCI bus to keep the buffer filled. However, if another EISA device requests data from memory, the buffer must be flushed and filled again.
Buffers also introduce problems with data consistency. While data is buffered in the bridge, a bus agent and the processor may have different ideas about what is really in memory. When a bus master issues a read request through the bridge to a target memory range on the other side of the bridge, the bridge must balance between two conflicting goals: performance and data integrity. If the memory operation and transfer were optimized for performance, the bridge would preferably hold large blocks of prefetched data. However, if data is prefetched in large blocks but unused, the bridge must guard against providing stale data on a subsequent read request by a master. Additionally, prefetching large blocks of unused data hurts performance by wasting bus bandwidth. Thus, it is desirable to find a solution which both meets performance concerns and also guarantees data integrity.
Buses can also operate at d
Akin Gump Strauss Hauer & Feld & LLP
Beausoleil Robert
Compaq Computer Corporation
Phan Raymond N
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