Buffer metal layer

Details Buffer metal layer Buffer metal layer

2005-03-01

2005-03-01

Everhart, Caridad (Department: 2825)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S669000, C438S121000, C257S692000, C257S786000

Reexamination Certificate

active

06861343

ABSTRACT:
An integrated circuit having a top passivation layer and bonding pads, where the improvement is a metal layer overlying all of the integrated circuit. The metal layer overlies the top passivation layer and is not in electrical contact with any of the bonding pads. In this manner, there is a structure that is added to the integrated circuit which has a relatively high thermal conductivity, and which also has a relatively high structural strength. With these two added properties, the occurrence of stress cracks, such as those induced by plastic molded packages, is reduced, and hot spots tend to be dissipated. Thus, the overlying metal layer tends to improve the reliability of the integrated circuit.

REFERENCES:
patent: 5336928 (1994-08-01), Neugebauer et al.
patent: 5534728 (1996-07-01), Kim et al.
patent: 5888889 (1999-03-01), Frisina et al.
patent: 5924006 (1999-07-01), Lur et al.
patent: 6303423 (2001-10-01), Lin
patent: 6380087 (2002-04-01), Gupta et al.

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