Buffer memory control apparatus

Details Buffer memory control apparatus Buffer memory control apparatus

1988-10-03

1991-09-17

Bowler, Alyssa H.

Static information storage and retrieval

Read/write circuit

Including signal comparison

36523008, 36523003, 36518905, 364900, G11C 700, G11C 11407

Patent

active

050501267

ABSTRACT:
Disclosed is a buffer memory control apparatus, in which a translation lookaside buffer for translating a logical address into a real address to make an access to a buffer storage has a logical address storage portion and a real address storage portion to each of which logical address bits are entered at its column. Column identifying address bits for the logical address storage portion partly overlap on column identifying address for a buffer address array for holding a real address to be supplied to the buffer storage, so that the buffer address array, the real address storage portion, and a comparator circuit for comparing the contents held by the buffer address array and the real address storage portion are divided into sections corresponding to the overlapping bits and the sections are suitably combined and arranged as circuits.

REFERENCES:
patent: 4218743, Hoffmann et al.
patent: 4561071 (1985-12-01), Hashimoto et al.
patent: 4577293 (1986-03-01), Matick et al.
patent: 4638426 (1987-01-01), Chang et al.
patent: 4943914 (1990-07-01), Kubo

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