Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
1998-07-21
2002-07-16
Peikari, B. James (Department: 2186)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S202000, C710S056000
Reexamination Certificate
active
06421770
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a buffer memory configuration, which is disposed between a data transmitter and a data receiver for the purpose of data communication, which is connected to the transmitter and the receiver via signal lines, which includes at least one memory for data buffering, and which has a memory management unit that controls reading from and writing to the memory via an address/data bus.
Buffer memories of this type are generally known as first-in, first-out memories (FIFO). The implementation of such a FIFO is described, for example, in
Electronic Circuits: Design and Applications
, U. Tietze and Ch. Schenk, Springer-Verlag, Berlin 1991, pp. 254-262.
A FIFO is a special form of a shift register. The common feature of such a shift register is that the data appear at the output in the same order as they were entered at the input: the first word read in (first-in) is thus read out first (first-out) as well. In contrast to a shift register, however, this operation can take place fully synchronously in a FIFO, i.e., the read-out clock is decoupled from the read-in clock.
In modern FIFOs, the data are no longer shifted, rather input and output addresses are specified in a memory module by means of two pointers, the so-called write pointer and the read pointer. In that case, the write pointer points to the first free address, while the read pointer points to the last address occupied. The pointers are usually realized by simple counters. The memory module is typically a random access memory (RAM).
A further FIFO of the generic type is described in German Published, Non-Proscuted Patent Application DE 44 33 692 A1.
FIG. 1
of that application shows such a FIFO, in which a sector of a memory area, which may be arranged in a random access memory (RAM), for example, is mapped. The addressed memory area in this case comprised addresses
22
,
23
, . . .
31
. In
FIG. 1A
, the data words D
1
-D
4
are written to the memory locations having the addresses
24
,
25
,
26
and
27
. The read pointer RP points to the memory location having the address
24
and the write pointer WP to the memory location having the address
28
.
If two further data words are then intended to be written to the queue (D
5
and D
6
), then the data word D
5
is written to the memory location having the address
28
and the data word D
6
to the memory location having the address
29
(FIG.
1
B). The write pointer WP is incremented by the number of written words. If data are then intended to be read from the memory locations, then reference is made via the read pointer RP to the memory location having the address
24
and the data word D
1
is read out.
After the reading operation (
FIG. 1C
) the read pointer RP points to the memory location having the address
25
and the write pointer WP points to the memory location having the address
30
after the write operation. After the write and read operations, the new data content of the queue comprises the data words D
2
-D
6
. The data words are buffer-stored in successive memory locations.
The disadvantage of such memory processing of a buffer memory is that memory locations in the buffer memory which have just been written to can only be read after the memory locations of the buffer memory which were written to chronologically before the memory location have been read. This is disadvantageous particularly when, in the buffer memory, only the data content of a few memory locations ever changes but the data content of the remaining memory locations mainly remains the same. Such a buffer memory architecture is thus very inflexible and the read-out is thus extremely time-consuming.
The following problem also frequently arises: the data transmitter, for example the bus, is inactive. If the bus is activated, then very large data packets must be written all at once to the buffer memory in a very short time. The data receiver, for example the central processing unit, however, frequently has a very much higher clock frequency than the data transmitter and, consequently, can read data from the buffer memory very much more rapidly than the data transmitter can write data thereto. As a result, the performance of the buffer memory is limited by the size of the buffer memory and the capability of the data transmitter to write data packets to the buffer memory as fast as they are read by the data receiver.
However, a FIFO buffer memory architecture according to the prior art only ever allows a data packet which maximally corresponds to the size of the buffer memory to be read by the data transmitter before the buffer memory can be written to again by the data transmitter. This processing procedure is very slow and, moreover, drastically limits the performance of the entire system.
In order to increase the performance of a buffer memory, therefore, it is necessary to provide a very large memory module (RAM) as buffer memory which can completely hold the volume of data to be transferred. This is exceedingly cost-intensive, however, particularly in the case of a microprocessor.
In the case of the data packets which are transmitted directly in succession by the data transmitter, it is frequently the case that only a few individual items of data change while the remaining data remain the same. This is the case, for example, with a data mask, a data form or the like. However, in a buffer memory of the generic type, the total volume of data is always written to the memory and then also read out again in its entirety. This is exceedingly complicated and takes a very long time as well.
Furthermore, with the existing FIFO memory architecture it is not possible simultaneously to write data to the memory and read data from the memory.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a buffer memory configuration, which overcomes the above-mentioned disadvantages of the prior art devices and methods of this general type and which is characterized by a more flexible, powerful buffer memory architecture.
With the foregoing and other objects in view there is provided, in accordance with the invention, a buffer memory configuration, comprising:
a data transmitter, a data receiver, and a buffer memory connected for data communication signal lines between the data transmitter and the data receiver;
the buffer memory including a memory for data buffering, an address/data bus connected to the memory, and a memory management unit controlling reading from and writing to the memory via the address/data bus;
the memory being mappable onto an address space exactly half as large as the memory, a first half of the memory defining a first memory page and a second half of the memory defining a second memory page, each address in the address space being assigned a respective memory location on each of the memory pages; and
the memory management unit generating a significant bit assigning in each case the two memory locations having the same address to the address space of the first memory page and to the address space of the second memory page.
In accordance with an added feature of the invention, the data transmitter and the data receiver are a respective one of a bus with a multiplicity of bus lines and a central processing unit, each of the bus and the central processing unit being operable as the data transmitter and the data receiver.
In accordance with an additional feature of the invention, the memory has at least one end point, each the end point being assigned a base address and an end address, and each the end point being adapted to occupy either memory locations of the first memory page or memory locations of the second memory page or memory locations of the first and second memory pages with the same addresses.
In accordance with another feature of the invention, the end points are adapted to store therein at least one data packet each having at least a data size of an individual memory location.
In accordance with a further feature of the invention, an end address of an end point is defined by a m
Barrenscheen Jens
Fenzl Gunther
Huch Martin
Infineon - Technologies AG
Peikari B. James
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