Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate
2006-09-19
2006-09-19
Shin, Christopher (Department: 2181)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
C710S033000, C710S022000, C710S006000, C710S310000, C370S412000, C370S429000
Reexamination Certificate
active
07111092
ABSTRACT:
A buffer-management technique efficiently manages a set of data buffers accessible to first and second devices interconnected by a split transaction bus, such as a Hyper-Transport (HPT) bus. To that end, a buffer manager controls access to a set of “free” buffer descriptors, each free buffer descriptor referencing a corresponding buffer in the set of data buffers. Advantageously, the buffer manager ensures that the first and second devices are allocated a sufficient number of free buffer descriptors for use in a HPT data path protocol in which the first and second devices have access to respective sets of free buffer descriptors. Because buffer management over the HPT bus is optimized by the buffer manager, the amount of processing bandwidth traditionally consumed managing descriptors can be reduced.
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U.S. Appl. No. 10/818,670, filed Apr. 6, 2004, entitled Hypertransport Data Path Protocol, by Mitten et al.
HyperTransport Technology Consortium, HyperTransport I/O Link Specification, Rev. 1.10, Aug. 25, 2003.
Barach David Richard
Hoult Kent
Mitten John W.
Potter, Jr. Kenneth H.
Riedle Christopher G.
Cesari and McKenna LLP
Cisco Technology Inc.
Shin Christopher
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