Buffer management architecture and method for an infiniband...

Details Buffer management architecture and method for an infiniband... Buffer management architecture and method for an infiniband...

2005-06-07

2005-06-07

Sparks, Donald (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Memory configuring

C711S173000, C711S217000, C718S105000, C718S104000, C370S389000, C370S235000

Reexamination Certificate

active

06904507

ABSTRACT:
An architecture and method for dynamically allocating and deallocating memory for variable length packets with a variable number of virtual lanes in an Infiniband subnetwork. This architecture uses linked lists and tags to handle the variable number of Virtual Lanes and the variable packet sizes. The memory allocation scheme is independent of Virtual Lane allocation and the maximum Virtual Lane depth. The disclosed architecture is also able to process Infiniband packet data comprising variable packet lengths, a fixed memory allocation size, and deallocation of memory when packets are either multicast or unicast. The memory allocation scheme uses linked lists to perform memory allocation and deallocation, while tags are used to track Infiniband subnetwork and switch-specific issues. Memory allocation and deallocation is performed using several data and pointer tables. These tables store packet data information, packet buffer address information, and pointer data and point addresses. The tags allow the memory allocation and deallocation process to correctly handle good and bad packets, as well as successive blocks within a data packet.

REFERENCES:
patent: 2001/0043564 (2001-11-01), Bloch et al.
patent: 2003/0193894 (2003-10-01), Tucker et al.
patent: 2003/0200315 (2003-10-01), Goldenberg et al.
patent: 2003/0223435 (2003-12-01), Gil
patent: 2004/0001487 (2004-01-01), Tucker et al.
Sancho, et al., “Effective Methodology for Deadlock-Free Minimal Routing in Infiniband Networks”, © 2002 IEEE, p. 1-10.

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