Buffer for integrated circuit pads

Details Buffer for integrated circuit pads Buffer for integrated circuit pads

1998-11-13

2000-06-13

Tokar, Michael

Electronic digital logic circuitry

Interface

Current driving

326121, 326 36, 326112, 326 27, H03K 190175, H03K 19094, H03K 1716

Patent

active

06075382&

ABSTRACT:
The present invention relates to a buffer for logic signals including a MOS output transistor of a first conductivity type connected by its source to a first supply potential, the drain of this transistor forming an output terminal of the buffer; a control transistor for controlling the output transistor connected between the gate of the output transistor and a second supply potential; a third transistor of the first conductivity type connected between the gate of the output transistor and the first supply potential and controlled to maintain the gate-source voltage of the buffer close to a threshold voltage so that the output transistor operates as a current generator; and a fourth transistor connected to render floating the gate of the third transistor when the potential on the output terminal is close to the first supply potential.

REFERENCES:
patent: 4825099 (1989-04-01), Barton
patent: 5329177 (1994-07-01), Nagai
patent: 5451861 (1995-09-01), Giebel
patent: 5455522 (1995-10-01), Jones
patent: 5656960 (1997-08-01), Holzer
patent: 5904618 (1999-06-01), Mattos
patent: 5926056 (1999-07-01), Morris et al.
patent: 5929668 (1999-07-01), Kim
patent: 5973512 (1999-10-01), Baker

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