Buffer for contact circuit

Details Buffer for contact circuit Buffer for contact circuit

2003-05-13

2004-10-19

Le, Don (Department: 2819)

Electronic digital logic circuitry

Interface

Supply voltage level shifting

C326S083000, C326S058000

Reexamination Certificate

active

06806735

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to a buffer, for example for a contact card. The invention is particularly related to a contact card using a power supply potential VDD
1
different from a power supply potential VDD
2
used by a reader with which the card communicates.
BACKGROUND OF THE INVENTION
A contact card C
1
(
FIG. 1
) generally comprises an integrated circuit CI grouping together all the electronic circuits capable of performing all the functions of the card. The circuit CI is connected to at least one contact pad or terminal PAD. When the card is used, the contact terminal/terminals of the card come into contact with one of the corresponding terminals of the card reader into which the card is inserted. A pad or terminal PAD can be used as input terminal for the circuit CI to receive data coming from the reader C
2
or as output terminal so that the circuit CI can transmit data to the reader. A same terminal PAD can also be used as input terminal for certain functions of the circuit CI and as output for other functions of the circuit CI.
When the card power supply potential VDD
1
is different from the reader power supply potential VDD
2
, then an input and/or output buffer has to be used between the terminal PAD and the circuit CI of the card to adapt the amplitude of the signals. An input buffer BE thus has the function of converting signals received from the reader, which range from 0 to VDD
2
, into signals ranging from 0 to VDD
1
that can be exploited by the circuit CI. Similarly, an output buffer BS has the function of converting signals to be transmitted to the reader and ranging from 0 to VDD
1
into signals ranging from 0 to VDD
2
that are exploitable by the card reader.
When a terminal PAD is used as input and output, the input and output buffers should not disturb each other at the common point at the terminal PAD. To this end, in particular, the output buffer BS should have a high impedance output when it is not used. In one example, we consider a card powered by an internal power supply potential VDD
1
powering the card. This potential VDD
1
is lower than the potential VDD
2
powering the reader. The internal power supply potential VDD
1
powering the card is produced, by a known regulation circuit, from the potential VDD
2
received at an input of the card. An input buffer for a card of this kind is made according to known approaches using, in particular, inverters supplied with the potential VDD
1
. An output buffer for a card of this kind is shown in FIG.
2
. It includes two potential step-up circuits
10
,
20
and one tristate inverter
30
.
The potential step-up circuit
10
receives a logic control signal VAL that takes either of two values, 0 or VDD
1
, and it produces a logic signal HVAL of a higher level, taking two values:
HVAL=0 when VAL=0
HVAL=VDD
2
when VAL=VDD
1
.
In the example of
FIG. 2
, the potential step-up circuit
10
comprises two P type transistors T
1
, T
3
, two N type transistors T
2
, T
4
, and one simple inverter I
1
powered by VDD
1
. The transistors T
1
, T
2
are series-connected. The potential VDD
2
is applied to the source and the well of T
1
and the source of T
2
is connected to a ground of the circuit. The common drain of the transistors T
1
, T
2
is connected to the gate of T
3
. The transistors T
3
, T
4
are also series-connected. The potential VDD
2
is applied to the source and the well of T
3
, and the source of T
4
is connected to the ground of the circuit. The common drain of the transistors T
3
, T
4
is connected to the gate of T
1
and forms the output of the potential step-up circuit
10
at which the signal HVAL is produced. Finally the gate of T
2
is connected to the gate of T
4
via the inverter I
1
. The gate of T
2
forms the input of the step-up circuit to which the signal VAL is applied.
The step-up circuit
20
receives a logic signal DATA, taking either of two values, 0 or VDD
1
, and it produces a logic signal INT that is the inverse of the signal DATA but has a higher level. The signal INT thus takes two values:
INT=VDD
2
when DATA=0
INT=0 when DATA=VDD
1
.
The step-up circuit
20
is made in the same way as the step-up circuit
10
; a simple inverter I
2
powered by the potential VDD
2
has simply been added to the output of the step-up circuit
20
. The inverter
30
receives the validation signal HVAL and the data signal INT, which take either of two values, 0 or VDD
2
. The inverter
30
has an output terminal OUT connected to the terminal PAD of the card. The inverter
30
works as follows: it produces a logic signal HDATA that is the inverse of INT, e.g. the same logic value as DATA, at the output OUT when the signal HVAL is active (in the example equal to 0); its output OUT is at high impedance when the signal HVAL is inactive.
The inverter
30
has two P type transistors T
5
, T
6
, two N type transistors T
7
, T
8
and one simple inverter I
3
. The transistors T
5
, T
6
, T
7
, T
8
are series-connected between a ground of the circuit and a power supply terminal to which the potential VDD
2
is applied. The potential VDD
2
is applied to the wells of the transistors T
5
, T
6
and to the source of the transistor T
5
whose drain is connected to the source of T
6
. The source of T
8
is connected to the ground of the circuit and its drain is connected to the source of T
7
. The drains of the transistors T
6
, T
7
are connected together to the output OUT of the inverter
30
. The gates of the transistors T
5
, T
8
are connected together and receive the signal INT. Finally, the gate of T
6
is connected to the gate of T
7
via the inverter I
3
powered by VDD
2
. The gate of T
6
receives the control signal HVAL.
The inverter
30
works as follows. When HVAL=VDD
2
, the transistors T
6
, T
7
are off and the output OUT is at high impedance, whatever the value of INT and whatever the state of the transistors T
5
, T
8
. Conversely, when HVAL=0, the transistors T
6
, T
7
are on. Depending on the value of the signal INT, the transistor T
5
or the transistor T
8
is on and the logic signal HDATA, which is the inverse of the signal INT, is produced at the output OUT. The signal HDATA is finally identical to the signal DATA from a logic point of view, but is at a higher potential level. It must be noted that the signals HVAL and INT must necessarily reach the value VDD
2
to turn off the operation of the inverter
30
, and more specifically to turn off the transistor T
6
, whence the necessity of using the potential step-up circuits
10
,
20
.
The buffer of
FIG. 2
has the drawback of using a large number of transistors. Indeed, given that a simple inverter (like I
1
, I
2
or I
3
) is made from a P type transistor and an N type transistor that are series-connected, it is necessary to use a total of 20 transistors to make the buffer. The fact that the number of transistors is large naturally entails a large-sized circuit, and also substantial power consumption.
SUMMARY OF THE INVENTION
It is an object of the invention to make a buffer with a reduced number of transistors, to make a buffer that is smaller-sized and consumes less power than the prior art buffers having the same function.
This and other objects are attained by a buffer according to the invention that includes a logic gate to raise the potential level of input digital data having a first logic level (“
1
”) to a potential equal to a low power supply potential (VDD
1
), and to produce intermediate data if a validation signal is active. The intermediate data has a first logic level (“1”) whose potential is equal to a high power supply potential (VDD
2
), and the intermediate data is logically inverse to the input data. The buffer also includes a tristate inverter to produce output data, at an output, that are logically inverse to the intermediate data if the validation signal is active and having its output OUT at high impedance if this is not the case.
A buffer according to the invention has the same function as a prior art equivalen

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