Buffer/driver circuits

Details Buffer/driver circuits Buffer/driver circuits

2005-12-13

2005-12-13

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Output switching noise reduction

C326S024000, C326S081000, C326S083000, C326S086000

Reexamination Certificate

active

06975134

ABSTRACT:
A buffer/driver having large output devices for driving multiple loads is configured with three parallel paths. The first logic path is made of small devices and is configured to provide the logic function of the buffer/driver without the ability to drive large loads. Second and third logic paths have the logic function of the first logic path up to the last inverting stage. The last inverting stage in each path is a single device for driving the logic states of the buffer output. The second and third logic paths have power-gating that allows the input to the pull-up and pull-down devices to float removing gate-leakage voltage stress. When the second and third logic paths are power-gated, the first logic path provides a keeper function to hold the logic state of the buffer output. The buffer/driver may be an inverter, non-inverter, or provide a multiple input logic function.

REFERENCES:
patent: 5497105 (1996-03-01), Oh et al.
patent: 6100729 (2000-08-01), Nagano et al.
patent: 6198308 (2001-03-01), Morrill
patent: 6650152 (2003-11-01), Kawabata
Rafik S. Guindi et al. “Design Techniques for Gate-Leakage Reduction in CMOS in Circuits,”IEEE, 2003, 5 pages.

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