Buffer device for a clock enable signal used in a memory device

Details Buffer device for a clock enable signal used in a memory device Buffer device for a clock enable signal used in a memory device

2006-01-24

2006-01-24

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S189050, C365S233100

Reexamination Certificate

active

06990033

ABSTRACT:
Disclosed is a buffer device for a clock enable signal in a memory device that is used when the memory device escapes from a self-refresh mode. The buffer device includes a first buffer for comparing a clock enable signal with an external reference voltage in accordance with a self-refresh flag signal, a second buffer for outputting a signal corresponding to the self-refresh flag signal as the clock enable signal, a comparator for comparing the external reference voltage applied from an outside with an internal reference voltage internally generated, and a switching unit for selecting and outputting an output of the first buffer if the external reference voltage is higher than the internal reference voltage and selecting and outputting an output of the second buffer if the external reference voltage is lower than the internal reference voltage in accordance with an output signal of the comparator.

REFERENCES:
patent: 2003/0076726 (2003-04-01), Cowles et al.
patent: 2005/0195674 (2005-09-01), Jang

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