Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate
2011-01-04
2011-01-04
Park, Ilwoo (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
C710S305000, C712S029000, C257S208000
Reexamination Certificate
active
07865635
ABSTRACT:
A buffer device that transfers data and is shared by a plurality of CPU cores arranged in a symmetrically inverted manner about a predetermined reference line, each CPU core breaking up a data block into a plurality of data lines and outputting the data lines via a plurality of ports, includes a plurality of line buffers that correspond to the data lines and are connected to the ports in the CPU cores, wherein the line buffers are paired into line buffer groups, and the line buffers in each buffer group are arranged symmetrically about the reference line.
REFERENCES:
patent: 4962037 (1990-10-01), Jett et al.
patent: 5197145 (1993-03-01), Kitamura et al.
patent: 2004/0210738 (2004-10-01), Kato et al.
patent: 2-82330 (1990-03-01), None
patent: 11-167522 (1999-06-01), None
patent: 2000-188381 (2000-07-01), None
patent: 2001-51957 (2001-02-01), None
Japanese Office Action issued on Apr. 1, 2009 in corresponding Japanese Patent Application 2008-501541.
International Search Report for PCT/JP2006/303443, mailed Nov. 21, 2006.
Fujitsu Limited
Fujitsu Patent Center
Park Ilwoo
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