Buffer controller and management method thereof

Details Buffer controller and management method thereof Buffer controller and management method thereof

2006-02-14

2006-02-14

Nguyen, T (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S119000, C711S120000, C711S121000, C711S122000, C710S052000, C710S053000, C710S056000, C710S057000

Reexamination Certificate

active

07000073

ABSTRACT:
The invention provides a new linked structure for a buffer controller and management method thereof. The allocation and release actions of buffer memory can be more effectively processed when the buffer controller processes data packets. The linked structure enables the link node of the first buffer register to point to the last buffer register. The link node of the last buffer register points to the second buffer register. Each of the link nodes of the rest buffers points to the next buffer register in order until the last buffer register. This structure can effectively release the buffer registers in the used linked list to a free list.

REFERENCES:
patent: 5535197 (1996-07-01), Cotton
patent: 5633865 (1997-05-01), Short
patent: 5812775 (1998-09-01), Van Seters et al.
patent: 6108692 (2000-08-01), Van Seters et al.
patent: 6119254 (2000-09-01), Assouad et al.
patent: 6826354 (2004-11-01), Tezuka

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