Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
1999-03-11
2001-04-10
Santamauro, Jon (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S017000, C326S058000, C326S086000
Reexamination Certificate
active
06215328
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a buffer circuit for temporarily storing information transferred between computers, for example.
2. Description of Related Art
FIG. 12
is a circuit diagram showing a conventional buffer circuit. In
FIG. 12
, the reference numeral
1
designates an input terminal for inputting an input signal;
2
designates an input terminal for inputting EL disable signal (low (L) active signal) when halting the output of an output signal from an output terminal
11
; reference numerals
3
and
4
each designate an inverter for inverting a signal level;
5
designates a NAND circuit to which the input signal and the inverted signal from the inverter
4
are supplied;
6
designates a NOR circuit to which the input signal and the inverted signal from the inverter
3
are supplied;
7
designates a power supply;
8
designates a ground;
9
designates a P-channel transistor that is brought out of conduction when its gate potential is at a high (H) level, and into conduction when its gate potential is at a low (L) level;
10
designates an N-channel transistor that is brought into conduction when its gate potential is at a high (H) level, and out of conduction when its gate potential is at a low (L) level; and
11
designates the output terminal for outputting an output signal.
Next, the operation of the conventional buffer circuit will be described.
The buffer circuit of
FIG. 12
outputs from the output terminal
11
an L level signal when an L level input signal is supplied to the input terminal
1
, and an H level signal when an H level input signal is supplied to the input terminal
1
. Let us assume here that the disable signal to the input terminal
2
is always placed at the H level so as to enable the output signal to be output from the output terminal
11
, because only the operation of this case will be described here.
First, when the L level input signal is supplied to the input terminal
1
, the NAND circuit
5
is supplied with the L level input signal and the H level inverted signal as shown in
FIG. 13
, placing the gate potential of the P-channel transistor
9
at the H level. Accordingly, the P-channel transistor
9
is brought out of conduction, and the output terminal
11
is disconnected from the power supply
7
.
At the same time, when the L level input signal is supplied to the input terminal
1
, the NOR circuit
6
is supplied with the L level input signal and the L level inverted signal as shown in
FIG. 13
, placing the gate potential of the N-channel transistor
10
at the H level. Accordingly, the N-channel transistor
10
is brought into conduction, and the output terminal
11
is connected to the ground
8
.
Thus, when the L level signal is input to the input terminal
1
, the output terminal
11
is connected to the ground
8
, which will place the potential of the output terminal
11
at zero, thereby producing the L level output signal from the output terminal
11
.
Second, when the H level input signal is supplied to the input terminal
1
, the NAND circuit
5
is supplied with the H level input signal and the H level inverted signal as shown in
FIG. 14
, placing the gate potential of the P-channel transistor
9
at the L level. Accordingly, the P-channel transistor
9
is brought into conduction, and the output terminal
11
is connected to the power supply
7
.
At the same time, when the H level input signal is supplied to the input terminal
1
, the NOR circuit
6
is supplied with the H level input signal and the L level inverted signal as shown in
FIG. 14
, placing the gate potential of the N-channel transistor
10
at the L level. Accordingly, the N-channel transistor
10
is brought out of conduction, and the output terminal
11
is disconnected from the ground
8
.
Thus, when the H level signal is input to the input terminal
1
, the output terminal
11
is connected to the power supply
7
. This will place the potential of the output terminal
11
at the power supply level, thereby producing the H level output signal from the output terminal
11
.
Therefore, when the input signal rises from the L level to H level, the output signal also changes from the L level to H level. In this case, the voltage rising rate of the output signal is determined by the capacity of a load connected to the output terminal
11
and the on-resistance of the P-channel transistor
9
. An increase of the capacity of the load connected to the output terminal
11
will reduce the voltage rising rate, thereby increasing a delay time between the rise of the input signal to the H level and that of the output signal to the H level.
With the foregoing arrangement, the conventional buffer circuit can produce the output signal of the same level as the input signal. The buffer circuit, however, has a problem of an increasing delay time between the rise of the input signal and that of the output signal due to an increase of the capacity of the load connected to the output terminal
11
.
SUMMARY OF THE INVENTION
The present invention is implemented to solve the foregoing problem. It is therefore an object of the present invention to provide a buffer circuit capable of reducing the increase in the delay time due to the increase in the capacity of the load connected to the output terminal.
According to a first aspect of the present invention, there is provided a buffer circuit comprising: a first transistor that has its first terminal connected to a power supply, and its second terminal connected to an output terminal, and that is brought out of conduction when its gate potential is at a high level, and is brought into conduction when its gate potential is at a low level, a second transistor that has its first terminal connected to a ground, and its second terminal connected to the output terminal, and that is brought into conduction when its gate potential is at the high level, and is brought out of conduction when its gate potential is at a low level; a first gate potential control means for connecting a gate terminal of the first transistor to the power supply when the input signal is at the low level, and for connecting the gate terminal of the first transistor to the output terminal when the input signal is at the high level; and a second gate potential control means for connecting a gate terminal of the second transistor to the output terminal when the input signal is at the low level, and for connecting the gate terminal of the second transistor to the ground when the input signal is at the high level.
Here, the first gate potential control means may connect, when the input signal changes from the low level to the high level, the gate terminal of the first transistor to the ground after a feedback period has elapsed.
The second gate potential control means may connect, when the input signal changes from the high level to the low level, the gate terminal of the second transistor to the power supply after a feedback period has elapsed.
The first gate potential control means may comprise selecting means for selecting the feedback period.
The second gate potential control means may comprise selecting means for selecting the feedback period.
The first gate potential control means may comprise selecting means for selecting a feedback amount of the output signal to the gate terminal of the first transistor.
The second gate potential control means may comprise selecting means for selecting a feedback amount of the output signal to the gate terminal of the second transistor.
The first gate potential control means may connect, when a disable signal is input, the gate terminal of the first transistor to the power supply, and the second gate potential control means may connect, when the disable signal is input, the gate terminal of the second transistor to the ground.
REFERENCES:
patent: 5319252 (1994-06-01), Pierce et al.
patent: 5389834 (1995-02-01), Kinugasa et al.
patent: 5391939 (1995-02-01), Nonaka
patent: 5760620 (1998-06-01), Doluca
patent: 5973512 (1999-10-01), Baker
patent: 5-122049 (1993-05-
Burns Doane , Swecker, Mathis LLP
Mitsubishi Electric System LSI Design Corporation
Santamauro Jon
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