Buffer circuit which transfers data held in a first latch circui

Electronic digital logic circuitry – Interface – Current driving

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Details

326 17, 365205, H03K 190175, H03K 19094, G11C 700

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active

059260378

ABSTRACT:
A buffer circuit which can solve a problem of a conventional buffer circuit in that high speed data transfer is hindered because of parasitic capacitance of signal lines, which has an affect on the discharge time of inverters in a latch circuit of the buffer circuit, when the buffer circuit changes its state from a first term (non-transfer mode) to a second term (transfer mode). The buffer circuit solves this problem by pouring a current, which flows thereinto from a first signal line, into ground through a first PMOS transistor, a first NMOS transistor and a third NMOS transistor, and by pouring a current, which flows thereinto from a second signal line, into the ground through a second PMOS transistor, a second NMOS transistor and the third NMOS transistor.

REFERENCES:
patent: 4739499 (1988-04-01), Simpson
patent: 4804871 (1989-02-01), Walters, Jr.
patent: 4937480 (1990-06-01), Higuchi et al.
patent: 5228106 (1993-07-01), Ang et al.
patent: 5325335 (1994-06-01), Ang et al.
patent: 5508644 (1996-04-01), Branson et al.
patent: 5872736 (1999-02-01), Keeth

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