Buffer circuit having a P-channel output mosfet with an open dra

Details Buffer circuit having a P-channel output mosfet with an open dra Buffer circuit having a P-channel output mosfet with an open dra

1986-09-30

1987-06-30

Miller, S. D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307584, 307577, 307585, 307475, 307304, 357 239, 340784, 340785, 350332, H03K 500, H03K 1708, H03K 19092, H01L 2908

Patent

active

046773142

ABSTRACT:
A semiconductor integrated device and a method for manufacturing the same, the device comprising an internal semiconductor integrated circuit which includes N-MOS transistors, and a P-MOS output transistor having a source connected to a voltage power supply. The drain of the P-MOS transistor is connected to an output terminal and the output terminal is operatively connected to a device driven by the P-MOS transistor.

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Fink et al., Electronics Engineers' Handbook, McGraw-Hill, Inc., pp. 16-15 through 16-19, 1982, (Ex'er book).
Ishaq et al., "Self-aligned FET Gate Structure and Method", IBM Tech. Discl. Bull., vol 26, No. 6, pp. 2680-2681, 11/83.
Ogura et al., "Design and Characteristics of the Lightly Doped Drain Source IGFET", IEEE Transactions on Electron Devices, vol. ED-27, No. 8, pp. 1359-1367, Aug. 80.
IBM Technical Disclosure Bulletin, "DMOS Raster-Scan Plasma Panel Drivers", by Oleszek et al., vol. 21, No. 3, Aug. 1978, pp. 1096-1098.

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