Electronic digital logic circuitry – Tri-state
Reexamination Certificate
2002-05-29
2002-12-03
Chang, Daniel D. (Department: 2819)
Electronic digital logic circuitry
Tri-state
C326S058000, C327S112000, C365S194000
Reexamination Certificate
active
06489808
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a buffer circuit, and more particularly, to a buffer circuit capable of carrying out an interface with a high speed.
In general, a buffer circuit is known of which output electric potential has a tri-state which is represented by first through third states. In the first state, the output of the buffer circuit becomes a low (L) level. In the second state, the output of the buffer circuit becomes a high (H) level. In the third state, the output of the buffer circuit becomes a high impedance (Hiz). Such a buffer circuit may be called a tri-state buffer circuit.
In a first conventional tri-state buffer circuit, the output of the first conventional tri-state buffer circuit becomes the high impedance even if the input signal has a low or a high level. The state of the high impedance denotes the third state (tri-state) indicating that the output value is neither 1 nor 0. In other words, the buffer circuit is disconnected in the third state.
In a second conventional tri-state buffer circuit, the output of the second conventional tri-state buffer circuit becomes the high impedance even if the input signal has a high level.
However, it is difficult to transfer from one state to another state with a high speed as will be described later.
In order to improve the above-mentioned demerit, a first improved tri-state buffer circuit is disclosed in Japanese Patent Publication Tokkai Hei 7-321633 (321633/1995). In the first improved tri-state buffer circuit, it is possible to determine a potential level with a high speed and to reduce a consumption power when the output state becomes the high impedance.
In addition, a second improved tri-state buffer circuit is disclosed in Japanese Patent Publication Tokkai Hei 5-37321 (37321/1993). In the second improved tri-state buffer circuit, the potential level is set to an intermediate level by the movement of charges stored to a capacitance for a period of a potential except for the high impedance, when the output state becomes the high impedance.
Furthermore, a third improved tri-state buffer circuit is disclosed in Japanese Patent Publication Tokkai Syo 63-112893 (112893/1988). The third improved tri-state buffer circuit comprises an intermediate potential setting circuit. By the intermediate potential setting circuit, an intermediate potential is set without increasing a pass-through current.
Similarly, a fourth improved tri-state buffer circuit is disclosed in Japanese Patent Publication Tokkai Hei 4-245470 (245470/1992). In the fourth improved tri-state buffer circuit, the output state is driven to an opposite potential level once and the output state is thereafter set to the high impedance when the input state becomes a disabling state.
However, it is impossible to control the output state to only either one of the high and low levels in the first improved tri-state buffer circuit. In the second improved tri-state buffer circuit, it is difficult to design a capacitance in which charges are stored. In the third improved tri-state buffer circuit, an inverter of an output stage becomes short circuited and a consumption power is large. In the fourth improved tri-state buffer circuit, it is necessary to have a resistor for pull-up/pull-down. When the fourth improved tri-state buffer circuit is a semiconductor integrated circuit, it is difficult to provide the resistor on the semiconductor integrated circuit since a chip area increases, under the requirement that the integrated circuit be more miniaturized.
SUMMARY OF THE INVENTION
It is an object of this invention to provide a buffer circuit capable of carrying out interface with a high speed without restricting level control and without increasing consumption power.
It is another object of this invention to provide a buffer circuit capable of carrying out interface with a high speed without necessity of a difficult capacitance design and increase of a chip area.
Other objects of this invention will become clear as the description proceeds.
On describing a gist of this invention, it is possible to understand that a buffer circuit has a high-impedance function mode. The buffer circuit is for outputting a buffer output level.
According to this invention, the buffer circuit comprises buffer output control means for controlling the buffer output level to an opposite level in a moment before the buffer circuit becomes the high-impedance function mode. The opposite level is a level opposite to a present buffer output level.
REFERENCES:
patent: 4529895 (1985-07-01), Garverick
patent: 4933579 (1990-06-01), Isobe et al.
patent: 4983860 (1991-01-01), Yim et al.
patent: 5210449 (1993-05-01), Nishino et al.
patent: 5436865 (1995-07-01), Kitazawa
patent: 5654648 (1997-08-01), Mehekar
patent: 6201743 (2001-03-01), Kuroki
patent: 0 481 698 (1992-04-01), None
patent: 63-112893 (1988-05-01), None
patent: 04-150224 (1992-05-01), None
patent: 04-245470 (1992-09-01), None
patent: 05-037321 (1993-02-01), None
patent: 7-105696 (1995-04-01), None
patent: 07-321633 (1995-12-01), None
patent: 236174 (2002-07-01), None
Rhyne, Fundamentals of Digital Systems Design, 1973, NJ, pp. 70-71.
Chang Daniel D.
Whitham Curtis & Christofferson, P.C.
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