Buffer circuit, buffer tree, and semiconductor device

Details Buffer circuit, buffer tree, and semiconductor device Buffer circuit, buffer tree, and semiconductor device

2005-08-23

2005-08-23

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S083000, C326S086000

Reexamination Certificate

active

06933750

ABSTRACT:
A buffer circuit includes first and second transistors which are connected in series between first and second power supplies and which are controlled to be on/off based on values of signals at their control terminals are provided, in which a connection point between the two transistors is connected to an output terminal (OUT) and a control terminal of the first transistor is connected to an input terminal (IN), and a control circuit for performing on/off control over the second transistor based on an input signal from the input terminal (IN). The control circuit performs control so that when the input signal is at a second logic level corresponding to the second power supply, the second transistor is turned off, when the input signal goes to a first logic level corresponding to the first power supply, the second transistor is turned on to cause the output terminal (OUT) to a second power supply voltage, next, when the second transistor is turned off and then the input signal undergoes a transition from the first logic level to the second logic level and the first transistor switches from off to on, with the second transistor being kept off. A flip-flop is connected to the output terminal (OUT).

REFERENCES:
patent: 5661415 (1997-08-01), Aoki et al.
patent: 6181182 (2001-01-01), Stotz et al.
patent: 6310499 (2001-10-01), Radjassamy
patent: 6549039 (2003-04-01), Rosen
patent: 6577165 (2003-06-01), Cheung et al.
patent: 6696863 (2004-02-01), Yamamoto et al.
patent: 05-048410 (1993-02-01), None
patent: 08-321768 (1996-12-01), None
patent: 11-353066 (1999-12-01), None

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