Buffer circuit and bias circuit

Details Buffer circuit and bias circuit Buffer circuit and bias circuit

1995-12-04

1997-07-15

Westin, Edward P.

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Field-effect transistor

326 17, 326 34, 326 83, 327 67, 327313, 327323, H03K 190948, H03K 19017

Patent

active

056487347

ABSTRACT:
An object of the present invention is to provide a buffer circuit little sensitive to a deviation from a threshold voltage of each of transistors. In order to achieve the above object, the present invention provides a typical buffer circuit comprising the following components. Namely, the buffer circuit comprises a first transistor having a first terminal connected to a current source, a second terminal connected to a first node and a control electrode connected to a first input terminal; a second transistor having a first terminal connected to the current source, a second terminal connected to a second node and a control electrode connected to a second input terminal; a third transistor having a first terminal connected to a first source node, a second terminal connected to the first node and a control electrode connected to a first output terminal; a fourth transistor having a first terminal connected to the first source node, a second terminal connected to the second node and a control electrode connected to a second output terminal; a fifth transistor having a first terminal connected to the first output terminal, a second terminal connected to the first source node and a control electrode connected to the first node; and a sixth transistor having a first terminal connected to the second output terminal, a second terminal connected to the first source node and a control electrode connected to the second node.

REFERENCES:
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patent: 5045807 (1991-09-01), Ishihara et al.
patent: 5382846 (1995-01-01), Shigehara et al.
patent: 5486778 (1996-01-01), Lou
patent: 5488321 (1996-01-01), Johnson
Vu et al., "The Performance of Source-Coupled FET Logic Circuits that Use GaAs MESFET's", 23 (1988) Feb., No. 1, New York, NY, USA, 8107 I.E.E.E. Journal of Solid State Circuits.
Ishihara, N., "9GHZ Bandwidth, 8-20DB Controllable-Gain Monolithic Amplifier Using AIGAASS/GAAS HBT Technology", Electronic Letters, vol. 25, No. 19, Sep. 14, 1989.

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