Electronic digital logic circuitry – Interface – Logic level shifting
Reexamination Certificate
2000-12-01
2004-03-09
Cho, James H (Department: 2819)
Electronic digital logic circuitry
Interface
Logic level shifting
C326S033000, C326S083000
Reexamination Certificate
active
06703864
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a buffer circuit, and more patticularly to a PECL (Pseudo Emitter Coupled Logic) buffer circuit for use in electric input and output sections of an optical interface module.
2. Description of the Related Art
PECL signal levels which include a high level of +4 V and a low level of +3 V. are used particularly in optical interfaces between LSI circuits. Though no problems are posed on signal levels for connection between ECL circuits and connection between PECL circuits, it is difficult to provide a complete level assurance when PECL signal levels are generated by CMOS components because the range of PECL signal levels is narrow.
In recent years, high-speed optical interfaces for handling high frequencies of several tens MHz or higher have begun to be used as general-purpose interfaces, and there is a demand for low-cost high-speed optical interfaces with related ICs constructed as CMOS ICs. One PECL buffer circuit which satisfies such a demand is disclosed in Japanese patent Application laid-open No. 8-172350.
FIG. 1
of the accompanying drawings shows the disclosed PECL buffer circuit. As shown in
FIG. 1
, the PECL buffer circuit has input terminals
40
,
41
for being supplied with respective PECL signals that are complementary to each other. Input terminal
40
is connected to the gates of PMOS transistor
42
and NMOS transistor
44
. Input terminal
41
is connected to the gates of PMOS transistor
43
and NMOS transistor
45
. PMOS transistors
42
,
43
have respective sources connected to a power supply VEE (+4 V). The drain of PMOS transistor
42
is connected to the drain of NMOS transistor
44
, and the drain of PMOS transistor
43
is connected to the drain of NMOS transistor
45
. The sources of NMOS transistors
44
,
45
are connected to constant current source
50
that is connected to ground (GND). A current of 10 mA flows through constant current source
50
. Output pad
48
has a terminal connected to the drain of PMOS transistor
43
, and output pad
49
has a terminal connected to the drain of NMOS transistor
44
. The other terminals of output pads
48
,
49
are connected to respective terminals of load resistors
46
,
47
which are connected in series with each other and which each has a resistance of 50 &OHgr;.
Operation of the PECL buffer circuit shown in
FIG. 1
will be described below. For instance, a high-level signal of +4 V is applied to input terminal
41
and a low-level signal of 3 V is applied to input terminal
40
, PMOS transistor
42
and NMOS transistor
45
are turned on, causing a current of 10 mA to flow from output pad
49
to output pad
48
via load resistors
47
,
46
. Therefore, a potential difference of 1 V is developed between the opposite terminals of load resistors
47
,
46
. Output pad
49
maintains a high-level voltage of +4 V, whereas output pad
48
maintains a low-level voltage of +3 V. Conversely, when a low-level signal of −3 V is applied to input terminal
41
and a high-level signal of +4 V is applied to input terminal
40
, PMOS transistor
43
and NMOS transistor
44
are turned on, causing a current of 10 mA to flow from output pad
48
to output pad
49
via load resistors
46
,
47
. Therefore, output pad
49
maintains a low-level voltage of +3 V, whereas output pad
48
maintains a high-level voltage of +4 V. The buffer circuit serves as a differential output buffer circuit of CMOS components for outputting PECL signals. Actually, 3.3 V is applied for the high level signal and 0 V is applied for the low level signal, usually.
In the conventional PECL buffer circuit, a common level Vcom at junction node N between load resistors
46
,
47
tends to vary, and cannot sufficiently catch up with variations in the power supply voltage. Therefore, the components suffer variations, and when the power supply voltage varies, the level of the output signal from the PECL buffer circuit may possibly fall out of the PECL signal level range.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a buffer circuit which comprises CMOS components in view of power supply voltage fluctuations and which satisfies PECL signal levels.
According to the present invention, there is provided a buffer circuit for driving an optical module, comprising a current-drive-type driver circuit of CMOS components, and a common level generating circuit for supplying a common level to a pseudo emitter coupled logic signal outputted from the current-drive-type driver circuit.
The current-drive-type driver circuit comprises a first constant current source connected to a first power supply, a first MOS transistor of a first conductivity type having a source connected to the first constant current source and a gate for being supplied with a first input signal, a second MOS transistor of the first conductivity type having a source connected to the first constant current source and a gate for being supplied with a second input signal complementary to the first input signal, a third MOS transistor of a second conductivity type having a drain connected to the drain of the first MOS transistor and a gate for being supplied with the first input signal, a fourth MOS transistor of the second conductivity type having a drain connected to the drain of the second MOS transistor and a gate for being supplied with the second input signal, and a second constant current source connected between the sources of the third and fourth MOS transistors and a second power supply.
Preferably, the buffer circuit also has a first output terminal connected to the drains of the first MOS transistor and the third MOS transistor, a first resistor having a terminal connected to the first output terminal and another terminal connected to an output terminal of the common level generating circuit, a second output terminal connected to the drains of the second MOS transistor and the fourth MOS transistor, and a second resistor having a terminal connected to the second output terminal and the other terminal connected to the output terminal of the common level generating circuit.
Preferably, the common level has variations at a gradient which is substantially the same as the gradient of variations of a power supply voltage, and the common level lies intermediate between high and low levels of the pseudo emitter coupled logic signal substantially at all times.
The common level generating circuit comprises means for generating a first constant current in response to a constant potential, a third resistor having a terminal connected to a power supply, a second current mirror circuit for being supplied with the first constant current, the second current mirror circuit being connected to another terminal of the third resistor for outputting a voltage of the power supply, and a first voltage-follower-type operational amplifier for being supplying with a second constant current flowing through the third resistor and outputting the common level.
The means for generating the first constant current comprises a second voltage-follower-type operational amplifier for being supplied with the constant potential, a fourth resistor connected between a node which is set to the constant potential by the second voltage-follower-type operational amplifier and a ground power supply, for passing a third constant current therethrough, and a first current mirror for being supplied with the third constant current and outputting the first constant current.
The first current mirror circuit comprises a pair of transistors which have respective sizes identical to each other, the second current mirror circuit comprises a pair of transistors which have respective sizes identical to each other, and the third and fourth resistors have respective resistances identical to each other.
According to the present invention, there is also provided a buffer circuit comprising a first output terminal, a second output terminal, a first resistor connected between the first
Nakano Fumio
Takeuchi Jun-ichi
Cho James H
Dickstein Shapiro Morin & Oshinsky LLP.
NEC Electronics Corporation
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