Electronic digital logic circuitry – Interface – Supply voltage level shifting
Reexamination Certificate
2001-02-21
2002-05-07
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Supply voltage level shifting
C326S083000, C326S058000
Reexamination Certificate
active
06384632
ABSTRACT:
This application is based on Japanese Patent Application 2000-044863, filed on Feb. 22, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
A) Field of the Invention
This invention relates to a buffer circuit having an output terminal through which data can be transferred to and from an external device.
B) Description of the Related Art
In the art of a semiconductor integrated circuit, it is important to raise the accumulation of the circuit while reducing the power consumption. It is effective for reducing the power consumption of an integrated circuit to lower the voltage of a power supply. In a transition period from a conventional 5V power supply to a new 3.3V power supply, for example, a multi-voltage circuit is used, wherein some parts of the circuit are designed to be driven by the 5V power supply while others to be driven by the 3.3V power supply. When a signal is output from a 5V part to a 3.3V part in that kind of multi-voltage circuit, some problems may occur. When a higher voltage than the voltage of a power source is applied to an input terminal, a Silicon Controlled Rectifier (SCR) of p-n-p-n structure with PMOS and NMOS is turned on, resulting in a formation of a current leak path or a latch up. In some case, a large amount of electric current flows through the SCR, resulting in over heating of the semiconductor integrated circuits.
Japanese Patent Publication H07-79232 discloses a driver circuit shown in
FIG. 5
that solves those problems. Power source voltage VDD of this driver circuit is 3.3V, and when a high level (H-level) enabling signal EN is supplied to an enabling terminal
10
, data D supplied to a data input terminal
28
could be output from a data output terminal
24
. On the other hand, when an L-level (0V) enabling signal EN is supplied to an enabling terminal
10
, output impedance of the data output terminal
24
will be a state of high impedance. Therefore, a 5V signal can be supplied to a bus connected to the output terminal
24
. Moreover, this driver circuit is built in a P-type silicon substrate whereas N-channel transistors are formed on an N-well formed on the P-type silicon substrate. Especially N-channel transistors
30
,
32
,
36
and
38
are formed on the same N-well that is floating.
First, a case when an enabling signal is high level will be considered. In this case, an N-channel transistor
12
is turned on and so an N-channel transistor
34
is also turned on; therefore, gate voltage of a P-chancel transistor
32
will be at the L-level. The P-chancel transistor
32
will be turned on. Because gate voltage of an N-channel transistor
26
is maintained to be at the power source voltage VDD, the transistor
26
is also turned on. On the other hand, gate voltages of both of a P-channel transistor
30
and N-channel transistor
22
are inversion of the data D. Therefore, when the data D is at the high level, voltage of the data output terminal
24
will be at the high level, and when the data D is at the L-level, voltage of the data output terminal
24
would be at the L-level.
Next, a case when an enabling signal is at the L-level will be considered. In this case, an N-channel transistor
12
is turned off. The gate voltage of the N-channel transistor
22
will be at the L-level, and the N-channel transistor
22
will be turned off. Moreover, the gate voltage of the P-channel transistor
30
will be at the high level, and the P-channel transistor
30
will be turned off. Therefore, output impedance of the data output terminal
24
would be in a state of high impedance.
At that time, assumingly a switch
44
is turned on, and an output signal S with 0V L-level and 5V high level is supplied from an external device
42
driven at 5V to the driver circuit. If the threshold voltage of the P-channel transistor
30
is 0.7V and voltage of the signal S is 5V, the P-channel transistor
30
would be turned on. Then, voltage of a node B becomes 5V whereas the gate voltage of the P-channel transistor
36
is 0V; therefore, the transistor
36
will be turned on. Also, the P-channel transistor
32
will be turned off. By that, current flow to the side of a voltage source
28
(VDD) can be prevented.
Also, N-wells of the P-channel transistors
30
,
32
and
36
are auto-biased by parasitic diodes formed between their drains and the N-wells. Therefore, current feedback by the parasitic pnp transistors including N-wells and the P-type silicon substrate will be vanished.
By forming a P-channel transistor
38
, when the voltage of the data output terminal
24
is at the L-level, an N-well is always biased by the power supply voltage VDD. The formation of the P-channel transistor
38
minimizes the possibility that the parasitic pnp transistors turn on during the transition of the signal S from the L-level to the high level.
As said in the above, in the driver circuit shown in
FIG. 4
, because there are no paths for the current flow to the semiconductor substrate, the problem of latch up can be solved.
By the way, in the above-described driver circuit, chip sizes of the P-channel transistors
32
and
30
and the N-channel transistors
22
and
26
will be large if large output current needed when the data D is output from the data output terminal
24
because gate widths of the transistors have to be increased to derive large current from the transistors.
In a practical circuit, a plurality of transistors need to be connected in parallel to form each of the P-channel transistors
32
and
30
and the N-channel transistors
22
and
26
.
However, there are problems in the enlargement of the chip sizes because the large chip sizes increase cost of manufacturing and also decrease the productivity due to the large number of the elements needed for manufacturing.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a driver circuit that is small in chip size while eliminating paths for the current flowing to a semiconductor substrate.
According to one aspect of the present invention, there is provided a buffer circuit comprising: a data input terminal to which a data signal is input; an enabling terminal to which an enabling signal is input; an output terminal from which output data are output; a first power source terminal to which high potential voltage is supplied; a second power source terminal to which low potential voltage lower than said high potential voltage is supplied; a first N-channel transistor that is connected between said output terminal and said second power source terminal; a common bulk P-channel transistors group that comprises a first, a second, a third, a fourth and a fifth transistors formed on a common bulk region, wherein the first P-channel transistor that is connected between said first power source terminal and said output terminal, the second P-channel transistor that is formed between said output terminal and one node and comprises a gate electrode connected to said first power source terminal, the third P-channel transistor that comprises a first current terminal connected to said output terminal, a second current terminal connected to a gate electrode of said first P-channel transistor, and a gate electrode connected to said first power source terminal, the fourth P-channel transistor that is formed between said first power source terminal and said gate electrode of said first P-channel transistor and comprises a gate electrode of which is supplied an inverted signal of the enabling signal, and the fifth P-channel transistor that comprises a drain electrode connected to said bulk region, a source electrode connected to said first power source terminal and a gate electrode connected to said one node; a second N-channel transistor that is formed between said one node and said second power source terminal and comprises a gate electrode supplied an inverted signal of an enabling signal; and a logic circuit that inputs an inverted signal of said input signal to said gate electrodes of said first P-channel transistor and said first N-channel transistor
Chang Daniel D.
Pillsbury & Winthrop LLP
Tokar Michael
Yamaha Corporation
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