Buffer circuit

Details Buffer circuit Buffer circuit

2000-10-18

2002-01-08

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S113000, C365S189050, C365S230060

Reexamination Certificate

active

06337582

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a buffer circuit and more particularly, to a buffer circuit that suppresses fluctuation or deviation of the power supply voltage and the ground voltage caused by the logic state change of a specific signal, which is preferably used as an address buffer circuit outputting an output signal such as an address signal in a low impedance state to the memory section of a semiconductor memory device.
2. Description of the Related Art
FIG. 1
shows an example of the conventional address buffer circuits used for semiconductor memory devices.
As shown in
FIG. 1
, the prior-art address buffer circuit
102
is comprised of an input stage
104
, first, second, third, and fourth inverter circuits
106
,
108
,
110
, and
112
, an Address Transition Detection (ATD) circuit
114
, and a wave-synthesizing pulse generator circuit
116
. Only the configuration for one bit of address is shown in
FIG. 1
for the sake of simplification; however, it is needless to say that the circuit
102
actually includes a lot of the same configuration as shown in
FIG. 1
according to the bit count of address.
The input stage
104
is a two-input NOR gate comprising two p-channel Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs)
131
and
132
connected in series and two n-channel MOSFETs
133
and
134
connected in parallel. The source of the p-channel MOSFET
131
is connected to the power supply line applied with a supply voltage of V
cc
while the drain of the MOSFET
131
is connected to the source of the p-channel MOSFET
132
. The drain of the p-channel MOSFET
132
is connected to the coupled drains of the n-channel MOSFETs
133
and
134
. The coupled sources of the n-channel MOSFETs
133
and
134
are connected to the ground. The gates of the MOSFETs
132
and
133
are connected to each other, forming the first input terminal
104
a
of the input stage
104
. An address signal ADIN, which is an input signal of the buffer circuit
102
, is supplied from the outside of the circuit
102
to the first input terminal
104
a
. The coupled gates of the MOSFETs
131
and
134
form the second input terminal
104
b
of the input stage
104
. A chip enable signal CEB is supplied to the second input terminal
104
b
from the outside of the circuit
102
. The coupled drains of MOSFETs
132
,
133
, and
134
constitute the output terminal
104
c
of the input stage
104
.
When the chip enable signal CEB is at a specific logic level, the address signal ADIN is taken into the input stage
104
and the output signal having an opposite logic level to the signal ADIN is outputted at the output terminal
104
c
. The output signal thus outputted is then supplied to the fourth inverter circuit
112
.
The first, second, third, and fourth inverter circuits
106
,
108
,
110
, and
112
have substantially the same configuration. Therefore, the configuration of the fourth inverter circuit
112
is explained below and the detailed description about the first, second, third inverter circuits
106
,
108
, and
110
is omitted by adding the same reference symbols to those of the circuit
112
except for the suffix letters.
The fourth inverter circuit
112
is comprised of a p-channel MOSFET
135
a
and an n-channel MOSFET
136
a
whose drains are coupled together, which is a Complementary MOS (CMOS) inverter. The source of the MOSFET
135
a
is connected to the power supply line of V
cc
. The source of the MOSFET
136
a
is connected to the ground. The gates of the MOSFETs
135
a
and
136
a
are coupled together, forming the input terminal
112
a
of the circuit
112
. The input terminal
112
a
is connected to the output terminal
104
c
of the input stage
104
. The coupled drains of the MOSFETs
135
a
and
136
a
form the output terminal
112
b
of the circuit
112
.
The fourth inverter circuit
112
generates at the output terminal
112
b
an output signal having an opposite logic level to the output signal from the input stage
104
. The output signal of the circuit
112
thus generated is then supplied to the ATD circuit
114
as the ATD input signal ATDIN and at the same time, it is supplied to the second and third inerter circuits
108
and
110
. As shown in
FIG. 1
, the ATD input signal ATDIN is also supplied to specific circuits (not shown) provided outside the address buffer circuit
102
.
The second inverter circuit
108
, which has substantially the same configuration as the fourth inverter circuit
112
, has an input terminal 108a formed by the coupled gates of a p-channel MOSFET
135
b
and an n-channel MOSFET
136
b
and an output terminal
108
b
formed by the coupled drains thereof. The input terminal
108
a
is connected to the output terminal
112
b
of the fourth inverter circuit
112
. The circuit
108
generates at its output terminal
108
b
an output signal having an opposite logic level to the output signal from the fourth inverter circuit
112
supplied to the input terminal
108
a
. The output signal of the circuit
108
is the inverted address signal BAR, which is one of the two output signals of the address buffer circuit
102
. The signal BAR is then supplied to a decoder circuit or circuits (not shown) provided outside the buffer circuit
102
.
The third inverter circuit
110
, which has substantially the same configuration as the fourth inverter circuit
112
, has an input terminal
110
a
formed by the coupled gates of a p-channel MOSFET
135
c
and an n-channel MOSFET
136
c
and an output terminal
110
b
formed by the coupled drains thereof. The input terminal
110
a
is connected to the output terminal
112
b
of the fourth inverter circuit
112
. The circuit
110
generates at its output terminal
110
b
an output signal having an opposite logic level to the output signal from the fourth inverter circuit
112
supplied to the input terminal
110
a
. The output signal of the circuit
110
is then supplied to the first inverter circuit
106
.
The first inverter circuit
106
, which has substantially the same configuration as the fourth inverter circuit
112
, has an input terminal
106
a
formed by the coupled gates of a p-channel MOSFET
135
d
and an n-channel MOSFET
136
d
and an output terminal
106
b
formed by the coupled drains thereof. The input terminal
106
a
is connected to the output terminal
110
b
of the third inverter circuit
110
. The circuit
106
generates at its output terminal
106
b
an output signal having an opposite logic level to the output signal from the third inverter circuit
110
supplied to the input terminal
106
a
. The output signal of the circuit
106
is the address signal TRUE, which is the other of the two output signals of the address buffer circuit
102
. The signal TRUE is then supplied to the decoder circuit or circuits (not shown) provided outside the buffer circuit
102
.
The ATD circuit
114
is supplied with the ATD input signal ATDIN outputted from the fourth inverter circuit
112
. The circuit
114
detects the logic level change of the signal ATDIN (i. e., address transition) and then, outputs the ATD output signal ATDOUT to the wave-synthesizing pulse generator circuit
116
.
The pulse generator circuit
116
generates a data latch signal DTL including pulses varying from the logic high level to the logic low level based on the signal ATDOUT from the ATD circuit
114
, and outputs the signal DTL to specific circuits provided outside the buffer circuit
102
.
The address signal TRUE, which is outputted from the first inverter circuit
106
, has a waveform corresponding to that of the address signal ADIN supplied to the input stage
104
of the buffer circuit
102
. Also, the inverted address signal BAR, which is outputted from the second inverter circuit
108
, has an inverted waveform of the signal TRUE. In other words, the signal BAR has an inverted logic level to the signal TRUE. The address signal TRUE and the inverted address signal BAR are supplied to the memory section (not shown) located outside the buffer circuit
102
thr

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