Buffer chip and method for controlling one or more memory...

Details Buffer chip and method for controlling one or more memory... Buffer chip and method for controlling one or more memory...

2004-03-03

2008-11-04

Nguyen, Tanh Q (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output command process

C710S001000, C710S020000, C710S036000, C710S040000, C710S052000, C710S054000, C710S058000, C710S059000, C710S062000, C710S063000, C710S064000, C710S071000, C710S072000, C710S073000, C710S074000, C711S100000, C711S150000, C711S151000, C711S154000, C711S167000, C711S168000, C711S169000

Reexamination Certificate

active

07447805

ABSTRACT:
A buffer chip having a first data interface for receiving a data item which is to be written and for sending a data item which has been read, having a conversion unit for parallelizing the received data item and for serializing the data item which is to be sent, having a second data interface for writing the parallelized data item to a memory arrangement via a memory data bus and for receiving the data item read from the memory arrangement via the memory data bus; having a write buffer storage for buffer-storing the data item which is to be written, having a control unit in order, after reception of a data item which is to be written via the first data interface in line with a write command, to interrupt the data from being written from the write buffer storage via the second data interface upon a subsequent read command.

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