Buffer bypass circuit for reducing latency in information...

Details Buffer bypass circuit for reducing latency in information... Buffer bypass circuit for reducing latency in information...

2007-11-13

2007-11-13

Lee, Christopher E. (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S309000, C710S313000, C370S229000

Reexamination Certificate

active

10767001

ABSTRACT:
A buffer bypass circuit for reducing latency in information transfers to a bus is described. Access to the bus is governed by a bus arbiter employing a bus parking scheme. The buffer bypass circuit comprises a multiplexer and logic configured such that the information to be transferred is either buffered in a buffer if a grant generated by the bus arbiter indicates that the bus is unavailable, or transferred directly to the bus if the grant indicates that the bus is available and the buffer is empty at the time.

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