Buffer apparatus with data insertion control function,...

Details Buffer apparatus with data insertion control function,... Buffer apparatus with data insertion control function,...

1999-06-22

2002-05-21

Yoo, Do Hyun (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C710S052000

Reexamination Certificate

active

06393532

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a buffer apparatus with an insertion data control function, an insertion data controlling method, and a data insertion apparatus with data insertion control function. More particularly, the invention relates to a buffer apparatus with a data insertion control function, an insertion data controlling method, and a data insertion apparatus with a data insertion control function, all of which are suitable for insertion of different types of OAM (Operation, Administration, and Maintenance) cells, which are used in ATM (Asynchronous Transfer Mode), one communication system in broadband ISDN, into a transmission medium.
2. Description of the Related Art
In an ATM communication network, as is well known, ATM cells (OAM cells) are generated according to purposes, such as maintenance, administration, and control of the network. In insertion of the generated cells into an ATM communication highway (transmission medium), a buffer is used to wait an idle cell available for the insertion so as to avoid erroneous modification to a user communication cell (user cell).
Suppose that generated (to be inserted) are different types of ATM cells [such as AIS (Alarm Indication Signal) cell, FERF (Far End Receive Failure) cell, RDI (Remote Defect Indication) cell, and LB (Loop Back) cell]. In such a case, there is a possible method in that, as shown in
FIG. 27
, insertion buffers
20
-
1
to
20
-n are prepared corresponding to cell types #1 to #n (where n: natural number of 2 or more, and of the order, at most, of 10 or less with the current state of the art), and are connected in parallel with an ATM communication highway
5
, thereby carrying out the cell insertion.
In
FIG. 27
, reference numerals
6
-
1
to
6
-n denote cell information generating sections for generating information for the cell types (OAM cell types) #1 to #n (hereinafter referred to as cell generating information), and reference numerals
7
′-
1
to
7
′-n denote cell assembling/inserting sections for assembling cells of the cell types #1 to #n from information generated in the cell information generating sections
6
-
1
to
6
-n to be temporarily held in the insertion buffers
20
-
1
to
20
-n, and inserting the resultant cell into an idle portion of a cell flow on the ATM communication highway
5
.
A more specific description will now be given of the operation of the buffer apparatus shown in FIG.
27
. The cell assembling/inserting section
7
′-i (where i: 1 to n) keeps monitoring whether or not an idle cell (insertable slot) is available on the ATM communication highway
5
, and finds the idle cell to post a message to this effect (insertability information) to the corresponding insertion buffer
20
-i.
The insertion buffer
20
-i receiving the message transfers, if cell generating information waiting insertion is held therein, cell generating information of cell type #i (hereinafter referred to as cell generating information #i) to be subsequently inserted to the posting cell assembling/insertion section
7
′-i. In such a way, the cell assembling/insertion section
7
′-i assembles an ATM (OAM) cell of cell type #i (hereinafter sometimes described as cell #i) from the cell generating information #i received from the insertion buffer
20
-i, and changes the idle cell into the assembled cell #i, thereby carrying out the cell insertion into the ATM communication highway
5
.
That is, in the device shown in
FIG. 27
, the cell assembling/insertion sections #i carry out the cell insertion sequentially from the upstream of the ATM communication highway
5
(from the left-hand side of FIG.
27
).
Next, a detailed description will now be given of a configuration of the insertion buffer
20
-i. Suppose that input (stored) is only one cell type (cell generating information) #i, and only one output line [physical line (associated with, for example, an ATM exchange)] is handled by the ATM communication highway
5
. In this case, as shown in
FIG. 28
, each insertion buffer
20
-i includes a memory
201
of FIFO (First-In First-Out) type in which write and read addresses can be administered by simple increments of read and write pointers.
In the insertion buffer
20
-i, when the cell generating information #i is input from the cell information generating section
6
-i, the cell generating information #i is written on an address area (shown by reference numeral a
6
in
FIG. 28
) indicated by the write pointer, thereafter incrementing the write pointer. On the other hand, when idle cell (insertability) information is received from the cell assembling/insertion section
7
′-i, the contents (cell generating information #i) of an address area (shown by reference numeral a
2
in
FIG. 28
) pointed by the read pointer are read and transferred to the cell assembling/insertion section
7
′-i, thereafter incrementing the read pointer. As a result, the written information are read out sequentially from first one, and are sequentially transferred to the cell assembling/insertion section
7
′-i.
If input is one cell type (cell generating information) #i and a plurality of output lines (L output lines, where L: natural number of 2 or more) are handled, a band control is needed for each line so that the insertion buffer
20
-i must be operated independently for each line. However, a mass memory is required to mount for each line the memory
201
described with reference to FIG.
28
. For multiple line effect, it is general to employ a shared buffer configuration in which an insertion buffer memory
202
is shared by the lines as shown in FIG.
29
.
In
FIG. 29
, reference numeral
203
denotes an idle address administration section,
204
is a pointer chain memory, and
205
is a buffer controller. In this case, at least, the pointer chain memory
204
has the same address configuration as that of the insertion buffer memory
202
. Further, the buffer controller
205
controls I/O of the insertion buffer memory
202
according to a pointer chain system using the pointer chain memory
204
.
A description will now be given of the write process to the insertion buffer memory
202
. For example, when cell generating information #i for a line numbered
1
is input from the cell information generating section
6
-i, the buffer controller
205
receives from the idle address administration section an address (for example, address a
0
) which is currently in an “idle” state, and writes the received cell generating information #i onto an area at the address a
0
. Subsequently, the idle address administration section
203
sets the used address a
0
to a “busy” state.
Next, since four (not zero) cells are stored for the line numbered
1
, the buffer controller
205
changes to the current write address (a
0
) an address (a
9
) of the pointer chain memory
204
corresponding to a tail pointer (shown by reference numeral a
9
in FIG.
29
), thereby incrementing the number of stored cells (from 4 to 5). Simultaneously, the tail pointer is changed to the current write address (a
0
), thereby updating the tail side of the pointer chain.
That is, the buffer controller
205
writes the cell generating information #i onto a certain address area of the insertion buffer memory
202
, thereafter writing the address (current write address) of the insertion buffer memory
202
at which the cell generating information #i is currently written onto the same address area of the pointer chain memory
204
as that of the insertion buffer memory
202
at which the previous write process was performed. Thus, the buffer controller
205
links, in a chain form, pointers (addresses) pointing respective write positions of the same buffer memory
202
at which the cell generating information #i are written to create a pointer chain.
If the number of stored cells is zero, the current write address becomes a starting point of the pointer ch

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