Buffer allocation for split data messages

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories

Reexamination Certificate

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C711S153000, C711S160000, C711S173000

Reexamination Certificate

active

11157321

ABSTRACT:
A technique to store a plurality of addresses and data to address and data buffers, respectively, in an ordered manner. More particularly, one embodiment of the invention stores a plurality of addresses to a plurality of address buffer entries and a plurality of data to a plurality of data buffer entries according to a true least-recently-used (LRU) allocation algorithm.

REFERENCES:
patent: 4078254 (1978-03-01), Beausoleil et al.
patent: 4458310 (1984-07-01), Chang
patent: 4905141 (1990-02-01), Brenza
patent: 5025366 (1991-06-01), Baror
patent: 5588136 (1996-12-01), Watanabe
patent: 6178481 (2001-01-01), Krueger et al.

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