Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Counting – scheduling – or event timing
Reexamination Certificate
2009-05-22
2010-11-30
Tran, Vincent T (Department: 2115)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Counting, scheduling, or event timing
C717S168000, C717S169000, C717S174000, C717S176000
Reexamination Certificate
active
07844850
ABSTRACT:
According to one embodiment, an information processor comprises a flush memory which stores a main program for executing information processing by using time data acquired through the clock count operation and a sub-program for upgrading a version of the main program of the information processing, a storage memory which stores the time data, and an arithmetic processing unit which executes the main program in starting the processor and executes the sub-program in upgrading the version, wherein the arithmetic processing unit executes the sub-program so as to continue the clock count operation even during execution of the version upgrading, and when the upgrading has completed, restarts the main program so as to restart the clock count operation by using the time data stored in the storage upon an execution start caused by restarting the main program.
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Explanation of Non-English Language Reference(s).
Notice of Reasons for Rejection for the Japanese patent application No. 2008-135921 mailed by Japan Patent Office on Jul. 28, 2009.
Kabushiki Kaisha Toshiba
Knobbe Martens Olson & Bear LLP
Tran Vincent T
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