Broadcast system in disk array controller

Details Broadcast system in disk array controller Broadcast system in disk array controller

2000-03-13

2003-05-13

Yoo, Do Hyun (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S147000, C711S148000, C710S008000, C709S213000

Reexamination Certificate

active

06564294

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a disk array controller utilizing a shared memory type multiprocessor system and relates in particular to technology for broadcasting of information shared between processors.
2. Description of Related Art
A disk array controller utilizing a shared memory type multiprocessor system has a structure as shown in FIG.
3
. The controller shown in
FIG. 3
is comprised of a plurality of CPU-PK (packages)
301
, a shared memory package (SM-PK) #A
303
holding shared memories for storing control information, and a shared memory package (SM-PK) #B
304
, all connected by a shared memory bus
302
. Each CPU-PK (package) is connected to either a host computer or disk device. Each CPU-PK (package) has a plurality of CPU and each CPU performs data transmission from the disk device or the host computer, or controls data transmission to the disk device or the host computer utilizing control information stored in the memory. In this way, when each CPU is connected on a common bus, the information from each CPU is routed along the common bus so that information from a particular CPU is sent to all the other CPU and broadcasting can easily be performed.
Though not related to a disk array controller, Japanese Published Unexamined Patent Application No. 61-45647 discloses a multibroadcast system connected to a common bus for broadcasting.
SUMMARY OF THE INVENTION
In the disk array control with the common bus system shown in
FIG. 3
, access requests from CPUs inside a CPU-PK (package) are concentrated in one shared memory bus so that when additional CPU-PK (packages) are connected to the shared memory bus, bottlenecks occur in data transfer along the common bus and improving access to the shared memory becomes difficult.
Further, when use of high performance CPUs is attempted in the CPU-PK (package), the data transfer capacity of the common bus becomes a bottleneck versus the performance of these processors and matching the performance of these processors becomes difficult.
However, the problem of the shared memory method can be resolved by connecting access paths in a one to one ratio between the shared memory and the CPUs inside the CPU-PK (package) and a disk array controller with an access path structure utilizing a star connection.
The star connection method however, has nothing equivalent to the common bus for allowing information to flow from each CPU so that just as with the common bus method, broadcasting cannot be easily performed. This invention therefore has the object of providing a disk array controller with a star connection between a plurality of processors and the shared memory, and capable of broadcasting.
In order to achieve the above objects, the disk array controller of this invention has a plurality of processors to control the interface with the disk device or the host device, and along with a star connection and shared memory to store the control information, utilizes the following five methods.
Firstly, a method wherein a structure has common broadcast dedicated buses between processors;
Secondly, a method wherein a register is provided to store broadcast data in the shared memory controller and each processor reads the register data by means of a broadcast interruption signal output from the shared memory controller.
Thirdly, a method wherein a register is provided to store broadcast data in the shared memory controller, and the data is written by the shared memory controller in a broadcast register provided in the shared memory access I/F controller of each processor.
Fourthly, a method wherein switch mechanisms are connected between the access I/F from each processor within the shared memory controller or within the shared memory package (hereafter called PK), the switch mechanisms maintain a one-to-many connection, and data is written in a broadcast register within the shared memory I/F controller of each processor.
Fifthly, a method wherein a register is provided to store broadcast data in the shared memory controller, and data written by a processor in a register is read by register polling by other processors.


REFERENCES:
patent: 4410944 (1983-10-01), Kronies
patent: 6216179 (2001-04-01), Murata et al.
patent: 0444376 (1990-02-01), None
patent: 5816362 (1983-01-01), None
patent: 6145647 (1986-03-01), None

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