Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or...
Reexamination Certificate
2006-07-11
2006-07-11
Nguyen, Hiep T. (Department: 2187)
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
C711S143000, C711S144000
Reexamination Certificate
active
07076597
ABSTRACT:
A directory-based multiprocessor cache control scheme for distributing invalidate messages to change the state of shared data in a computer system. The plurality of processors are grouped into a plurality of clusters. A directory controller tracks copies of shared data sent to processors in the clusters. Upon receiving an exclusive request from a processor requesting permission to modify a shared copy of the data, the directory controller generates invalidate messages requesting that other processors sharing the same data invalidate that data. These invalidate messages are sent via a point-to-point transmission only to master processors in clusters actually containing a shared copy of the data. Upon receiving the invalidate message, the master processors broadcast the invalidate message in an ordered fan-in/fan-out process to each processor in the cluster. All processors within the cluster invalidate a local copy of the shared data if it exists and once the master processor receives acknowledgements from all processors in the cluster, the master processor sends an invalidate acknowledgment message to the processor that originally requested the exclusive rights to the shared data. The cache coherency is scalable and may be implemented using the hybrid point-to-point/broadcast scheme or a conventional point-to-point only directory-based invalidate scheme.
REFERENCES:
patent: 5261066 (1993-11-01), Jouppi et al.
patent: 5317718 (1994-05-01), Jouppi
patent: 5758183 (1998-05-01), Scales
patent: 5761729 (1998-06-01), Scales
patent: 5787480 (1998-07-01), Scales et al.
patent: 5802585 (1998-09-01), Scales et al.
patent: 5809450 (1998-09-01), Chrysos et al.
patent: 5875151 (1999-02-01), Mick
patent: 5890201 (1999-03-01), McLellan et al.
patent: 5893931 (1999-04-01), Peng et al.
patent: 5918250 (1999-06-01), Hammond
patent: 5918251 (1999-06-01), Yamada et al.
patent: 5923872 (1999-07-01), Chrysos et al.
patent: 5950228 (1999-09-01), Scales et al.
patent: 5964867 (1999-10-01), Anderson et al.
patent: 5983325 (1999-11-01), Lewchuk
patent: 6000044 (1999-12-01), Chrysos et al.
patent: 6014728 (2000-01-01), Baror
patent: 6038651 (2000-03-01), Van Huben et al.
patent: 6070227 (2000-05-01), Rokicki
patent: 6085300 (2000-07-01), Sunaga et al.
patent: 6189078 (2001-02-01), Bauman et al.
patent: 6751721 (2004-06-01), Webb et al.
Alpha Architecture Reference Manual, Third Edition, The Alpha Architecture Committee, 1998 Digital Equipment Corporation (21 p.), in particular pp. 3-1 through 3-15.
A Logic Design Structure For LSI Testability, E. B. Eichelberger et al., 1977 IEEE (pp. 462-468).
Direct RDRAM™ 256/288-Mbit(512Kx16/18x32s), Preliminary Information Document DL0060 Version 1.01 (69 p.).
Testability Features of AMD-K6™ Microprocessor, R. S. Fetherston et al., Advanced Micro Devices (8 p.).
Hardware Fault Containment in Scalable Shared-Memory Multiprocessors, D. Teodosiu et al., Computer Systems Laboratory, Stanford University (12 p.), 1977.
Cellular Disco: resource management using virtual clusters on shared-memory multiprocessors, K. Govil et al., 1999 ACM 1-58113-140-2/99/0012 (16 p.).
Are Your PLDs Metastable?, Cypress Semiconductor Corporation, Mar. 6, 1997 (19 p.).
Rambus® RIMM™ Module(with 128/144Mb RDRAMs), Preliminary Information, Document DL0084 Version 1.1 (12 p.).
Direct Rambus™ RIMM™ Module Specification Version 1.0, Rambus Inc., SL-0006-100 (32 p.), 2000.
End-To-End Fault Containment In Scalable Shared-Memory Multiprocessors, D. Teodosiu, Jul. 2000 (148 p.).
Kessler Richard E.
Lang Steve
Spink Aaron T.
Webb, Jr. David A. J.
Hewlett--Packard Development Company, L.P.
Nguyen Hiep T.
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