Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2001-01-08
2003-12-23
Mills, Gregory (Department: 1763)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C156S345350
Reexamination Certificate
active
06667242
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to the field of plasma etching of wafer-like objects held in a non-contact wafer holder and, more particularly, to a brim and gas escape structure around the circumference of the wafer reducing unstable and non-uniform plasma traverse near the wafer's edge, while deflecting plasma and etching debris from the wafer's edge and unetched face and providing additional means of controlling wafer etching in the edge region.
2. Description of Related Art
Numerous areas of technology require that a workpiece be held in position while processes are performed thereon. The processing of semiconductor wafers into integrated circuits requires the wafer to be held by a suitable holder without impeding the processing steps directed to the exposed flat surface of the wafer. Following production of the integrated circuits, wafer processing is generally not finished. In particular, many areas of technology (cell phones, smart cards and the like) require that the integrated circuit providing the internal intelligence for the device be very thin. It is typically inconvenient to fabricate the integrated circuits directly on a thin wafer as distortion, non-uniform processing, perhaps even rupture, may occur during the several processing steps typically required for integrated circuit fabrication. Therefore, it is common practice for a wafer containing numerous fully fabricated integrated circuits thereon to be thinned by means of etching from the reverse side of the wafer. Plasma etching is the typical method for wafer thinning. For economy of language we will refer to the “face” of the wafer and intend thereby the face undergoing (or destined to undergo) etching, resulting in thinning of the wafer. The “opposite face” of the wafer denotes the face of the wafer not undergoing etching, typically having the integrated circuits thereon and lying in close proximity to the wafer holder.
Several challenges must be met for successful wafer thinning by plasma etching. The wafer is (or soon becomes) very thin, rendering it susceptible to distortion. Distortion would generally lead to non-uniform etching, non-uniform heating of the wafer and potential damage to the integrated circuits lying on the reverse face of the wafer from that being etched. Thus, an important challenge to be met by a wafer holder is the ability to hold thin, easily distorted wafers in a flat position during etch. Of course, the wafer holder must not contact the exposed integrated circuits lying on the opposite face. Thus, non-contact support for a flexible wafer must be provided.
To be definite in our description of the invention, we will describe the common instance of the processing of semiconductor wafers as may typically occur in the production of integrated circuits or in wafer post-processing for thinning, etc. However, the processing of any wafer-like object in a non-contact holder is also a potential area of application for the present invention. Flat panel displays and other rectangular, circular, star-shaped or irregularly shaped planar objects may require processing by means of a non-contact holder. For economy of language we will refer to all such wafer-like objects herein as “wafers” recognizing that such objects may be large and need not be rectangular, circular or regular in shape. Since semiconductor wafers are expected to be an important area of application for the present invention, we will describe the primary features of the present invention in terms of semiconductor processing, not intending to limit the invention to this particular choice or particular example. Semiconductor wafers aptly illustrate the features of the present invention and permit obvious modification for use in processing other wafer-like objects.
The floating of a wafer above a layer of compressed gas is described in the work of Pirker (U.S. Pat. No. 5,896,877). The wafer is held in position by gravity while the air cushion prevents contact with the wafer holder.
Work of Siniaguine and Steinberg (PCT International Publication No. WO 97/45862) describes a non-contact holder for wafer-like objects in which a vortex of rotating air provides both the vacuum support for the wafer and the air cushion.
One challenge to be met by a non-contact wafer holder relates to preventing debris from the plasma etch from contaminating the integrated circuits on the opposite face of the wafer. More stringently, the wafer holder should also prevent debris from impacting the thin edge of the wafer. Non-contact support invariably implies a gap between the wafer and the holder. Etching debris clearly need to be kept out of this gap. Preferably, the etching debris should also be kept from the wafer edge. While not as serious a problem as debris contacting the opposite face of the wafer, edge contamination may lead to rejection of the particular integrated circuits lying on the contaminated regions of the edge thus, reducing yield.
Plasma etching of a wafer typically occurs by means of the wafer passing through a largely stationary plasma discharge. The plasma discharge tends to preferentially dwell on the leading and trailing edges of the wafer as the wafer passes through the discharge rather than uniformly traversing onto and off of the wafer. This can lead to non-uniform etching. The brim structure of the present invention is intended to provide for a smooth transition of the plasma discharge onto and off of the wafer, facilitating thereby uniform etching of the entire wafer including the edge portions thereof.
BRIEF SUMMARY OF THE INVENTION
The present invention comprises a brim surrounding a wafer or wafer-like object during plasma etching in a non-contact wafer holder. This brim is preferably 20 mm to 25 mm in width, approximately 1.3 mm thick and the gap is substantially constant throughout the circumference of the wafer. The gap is preferably approximately 0.5 mm for etching of integrated circuit wafers. A brim so dimensioned and configured will facilitate the plasma discharge in flowing smoothly onto and off of the wafer, avoiding thereby the plasma instability and non-uniform flow typically of conventional plasma etching near the edges of the wafer being etched. The brim of the present invention, by facilitating uniform and stable plasma flows, decreases non-uniform etching.
One embodiment of the present invention permits the brim to move in the axial direction from a position substantially aligned with the lower face of the wafer to a position typically 1 mm to 3 mm below the plane of the wafer. This permits the etching process to be controlled for more uniform and precise wafer etching as lowering the brim tends to shadow the edge region of the wafer from the plasma, reducing etching in the edge region while not significantly affecting etching in the central regions of the wafer.
Another embodiment of the wafer includes a barrier on the upper side of the brim, that is the side opposite the plasma. This barrier is directed upward from the brim at an oblique angle away from the wafer. This barrier contacts the upper surface of the brim so as to leave a protrusion or debris-collecting shelf on the upper interior portion of the brim. This shelf in combination with the upward oblique barrier deflects the plasma and debris from plasma etching away from the wafer. Debris is typically deposited on the shelf portion of the brim from which it is readily cleaned following the etching process.
Yet another embodiment of the present invention includes a baffle for controlling the vertical flow of gas exiting from the non-contact wafer holder. Additional control of the etching process (especially near the edge of the wafer) is obtained by adjusting the baffle to direct the gas flow to a greater or lesser degree in the direction towards the wafer holder versus escaping around the wafer's edge.
REFERENCES:
patent: 4340461 (1982-07-01), Hendricks et al.
patent: 5569350 (1996-10-01), Osada et al.
patent: 5698062 (1997-12-01), Sakamoto et al.
patent: 5900064 (1999-05-01), Kholodenko
pat
Berger Alex
Savastiouk Sergey
Siniaguine Oleg
MacArthur Sylvia R
MacPherson Kwok & Chen & Heid LLP
Mills Gregory
Shenker Michael
Tru-Si Technologies Inc.
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